S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 346

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

4. PIN DESCRIPTION
S1D15700 Series
9–4
Pin Name
X1 – X80
D
XSCL
LP
EIO1
EIO2
SHL
DOFF
FR
YD
V
V
V
V
0
3
EE
DD
0
, V
, V
– D
, V
2
5
,
3
SS
Power
supply
Power
supply
Power
supply
I/O
I/O
I/O
O
I
I
I
I
I
I
LCD drive segment (column) output
Display data input
Display data shift clock input
Display data latch clock input
• The display RAM data (specified by the low address shift register) is read
• For a specified low address, the contents of the write register are written
• Resets the enable control circuit.
Enable I/O
• Configured by SHL.
• Output is reset to HIGH by LP input. When the 80 bit display data is read,
• To connect in cascade format, connect these pins to the next level EIO.
Shift direction and input/output select input
• If the display data is entered in the input (D
Forced blank input
LCD AC drive signal input
Scan start input
• Rests the low address counter decoder.
• The number of scanned lines (number of low addresses) for the
LCD drive power input
LCD drive power input V
Logic power input
HIGH t4
The output changes with the LP’s trailing edge.
Reads the display data (D
edge.
into the latch with a leading edge, and the LCD display data is output.
in the display RAM. (At Data transfer mode)
the output falls to LOW automatically.
(a1, a2, a3, a4) (b1, b2, b3, b4) … (t1, t2, t3, t4), the relationship of the
display data and the segment output is as given in the table below.
In the LOW level, the segment output is forced to the V
The display RAM data is maintained.
display RAM is determined by the number of LP pulses, which are
input in one YD cycle.
V
V
V
LOW a1 a2 a3 a4 b1 b2 … s3 s4 t1 t2
SHL
DD
DD
SS
: connect to the system GND.
: connect to the system V
V
80 79 78 77 76 75 …
0
V
t3
2
t2 t1 s4 s3 … b2 b1 a4 a3 a2 a1
V
3
V
DD
5
EPSON
– V
Xn (SEG output)
0
V
– D
EE
EE
Function
CC
3
) into the data register with a trailing
pin.
6
5
3
, D
4
2
, D
3
1
, D
0
t3 t4
2
0
) in the order of
level.
1
O
1
I
EIO
O
2
I
Rev. 3.0
No. of
Pins
80
4
1
1
2
1
1
1
1
4
1
2