S1D10605 Epson Electronics America, Inc., S1D10605 Datasheet - Page 177

• Manufacturer Part Number: S1D10605
• Description: S1d15000 Series Lcd Driver With Ram
• Manufacturer: Epson Electronics America, Inc.

S1D15400 Series
Common Timing Generator
This circuit generates common timing and frame (FR)
signals from the basic clock CL. The “Select Duty
Cycle” command selects a duty cycle of 1/3 or 1/4.
Display Data Latch Circuit
This latch stores one line of display data for use by the
LCD driver interface circuitry. The output of this latch
is controlled by the “Display ON/OFF” and “Static
Driver ON/OFF” commands.
LCD Drive Circuit
The LCD driver circuitry generates the 77 4-level signals
used to drive the LCD panel, using output from the
display data latch and the common timing generator
circuitry.
Display Timing Generator
This circuit generates the internal display timing signal
using the basic clock OSC1, and the frame signal, FR.
FR is used to generate the dual frame AC-drive wave-
form (type B drive) and to lock the line counter and
common timing generator to the system frame rate.
OSC1 is used to lock the line counter to the system line
scan rate.
Oscillation Circuit
The oscillator is a low power RC oscillator whose fre-
quency of oscillation is determined by the value of the
feedback resistor R
cycle clock input via OSC1. If a slave S1D15400 is used,
its OSC2 input is connected to the OSC2 output of the
master driver.
• Oscillator mounted
*1 Oscillating freguency shifts to low freguency side
• External clock operation
6–12
when parasitic capacity gets larger, So Rf should be
smaller than the regular value.
f
or an externally generated 50% duty
V
DD
M/S
Clock originating
OSC1
(MPU)
CL
Master
Rf
*1
EPSON
OSC2
Reset Circuit
This circuit senses both the edge and the level of the
signal at the RES pin and uses this information to
• Initialization status
1. Display is off.
2. Display start line register is set to line 1.
3. Static drive is turned off.
4. Column address counter is set to address 0.
5. Page address register is set to page 0.
6. 1/4 duty is selected.
7. Forward ADC is selected (ADC command D0 is 0 and
8. Read-modify-write is turned off.
The input signal level at RES pin is sensed, and an MPU
interface mode is selected as shown on Table 1. For the
80-series MPU, the RES input is passed through the
inverter and the active high reset signal must be entered.
For the 68-series MPU, the active low reset signal must
be entered.
When the Reset command is issued, initialization items
2, 4 and 5 above are executed.
As shown for the MPU interface (reference example), the
RES pin must be connected to the Reset pin and reset at
the same time as the MPU initialization.
If the MPU is not initialized by the use of RES pin during
power-on, an unrecoverable MPU failure may occur.
*2 CMOS buffer is needed when connecting to more
ADC status flag is 1).
than two slave LSI.
*2
V
DD
V
SS
M/S
M/S
OSC1
S1D15400
OSC1
Open
Slave
OSC2
OSC2
Rev. 1.0
Slave
OSC2