STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 8

• Manufacturer Part Number: STE10-100A
• Description: Pci 10/100 Ethernet Controller With Integrated Phy
• Manufacturer: STMicroelectronics

Pin description
8/82
Table 1.
PCI bus interface
120,121
123,124
126,127
Pin no.
32~35
12,13
15,16
29,30
43,44
46,47
49,50
52,53
9,10
113
114
116
117
118
119
1,2
6,7
37
41
Pin description
AD-13~10
AD-31,30
AD-29,28
AD-27,26
AD-25,24
AD-23,22
AD-21,20
AD-19,18
AD-17,16
AD-15,14
PCI-CLK
AD-7, 6
AD-5,4
AD-3,2
AD-1,0
Name
INTA#
GNT#
REQ#
PME#
RST#
AD-9
AD-8
Type
O/D
OD
I/O
O
O
I
I
I
PCI interrupt request. STE10/100A asserts this signal when
one of the interrupt event is set.
PCI reset signal to initialize the STE10/100A. The RST signal
should be asserted for at least 100µs to ensure that the
STE10/100A completes initialization. During the reset period,
all the output pins of STE10/100A will be placed in a high-
impedance state and all the O/D pins are floated.
PCI clock input to STE10/100A for PCI bus functions. The
Bus signals are synchronized relative to the rising edge of
PCI-CLK PCI-CLK must operate at a frequency in the range
between 20MHz and 33MHz to ensure proper network
operation.
PCI bus granted. This signal indicates that the STE10/100A
has been granted ownership of the PCI bus as a result of a
bus request.
PCI bus request. STE10/100A asserts this line when it needs
access to the PCI Bus.
The power management event signal is an open drain, active
low signal. The STE10/100A will assert PME# to indicate that
a power management event has occurred.
When WOL (bit 18 of CSR18) is set, the STE10/100A is
placed in wake on LAN mode. While in this mode, the
STE10/100A will activate the PME# signal upon receipt of a
magic packet frame from the network.
In the wake on LAN mode, when LWS (bit 17 of CSR18) is
set, the LAN-wake signal follows HP’s protocol; otherwise, it
is IBM protocol.
Multiplexed PCI bus address/data pins
Description
STE10/100A