STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 74
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STE10-100A
Manufacturer Part Number
STE10-100A
Description
Pci 10/100 Ethernet Controller With Integrated Phy
Manufacturer
STMicroelectronics
Datasheet
1.STE10-100A.pdf
(82 pages)
- Current page: 74 of 82
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Electrical specifications and timings
74/82
Figure 16. PCI clock waveform
Table 21.
Table 22.
Tval(ptp)
Tsu(ptp)
Symbol
Symbol
Trst-clk
Trst-off
TX1C
TX1d
TX1p
TX1t
Tval
Tsu
Ton
Toff
Trst
Th
Th
L
X1 duty cycle
X1 period
X1 tolerance
X1 load capacitance
Clock to signal valid delay
(bussed signals)
Clock to signal valid delay
(point to point)
Float to active delay
Active to float delay
Input set up time to clock
(bussed signals)
Input set up time to clock
(point to point)
Input hold time from clock
Input hold time from clock
Reset active time after power
stable
Reset active time after clk
stable
Reset active to output float
delay
X1 specifications
PCI timing
0.2Vcc
Parameter
Parameter
0.475Vcc
0.4Vcc
0.6Vcc
Th
Tc
Test condition
Test condition
0.325Vcc
Tl
10,12
Min.
Min.
100
45
2
2
2
7
0
0
1
0.4Vcc, p-to-p
minimum
Typ.
Typ.
50
30
STE10/100A
Max.
Max.
+ / -
55
50
18
11
11
28
40
Units
Units
PPM
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
%
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