MEA-208 Zarlink Semiconductor, Inc., MEA-208 Datasheet - Page 4

• Manufacturer Part Number: MEA-208
• Description: 6+2 Ports Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2020 Series –
Ethernet Switch Chipset
1.2 Pin Assignment (Preliminary)
© 1998 Vertex Networks, Inc.
1999
Pin No(s).
Management Bus Interface
J25,K26,L24,K25,L26,
M24,L25,M26,N24,M25,
P24,N26,N25,R24,P26, P25
C26,D24,C25,E24,D26,
D25,F24,E26,E25,G24, F26
F25
H25
J24
G25
G26
H26
J26
K24
XpressFlow Bus Interface
C23,A23,B22,C22,A22
B21,D20,C21,A21,B20,
A20,C20,B19,A19,C19,
B18,A18,B17,C18,A17,
D17,B16,C17,A16,B15,
A15,C16,B14,D15,A14,
C15,B13
B12
A12
C14
C13
B23
A24
B24
A13
D13
Note:
Out-OD
P
I/O-OD
Output
I/O-TS
In-ST
Input
5VT
•
‚
ƒ
R
#
E
Active low signal
Input signal
Input signal with Schmitt-Trigger
Output signal (Tri-State driver)
Output signal with Open-Drain driver
Input & Output signal with Tri-State driver
Input & Output signal with Open-Drain driver
Input with 5V Tolerance
Output signal with programmable polarity.
Input or output pins with weak internal pull up resistors (50k to 100k Ohms each)
These pins are reserved for internal use only. They should be left unconnected.
L
I
P_D[15:0]
P_A[11:1]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
S_D[31:27] /
P_C[0:4]
S_D[26:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
M
Symbol
I
N
• CMOS Output
A
TTL I/O-TS (5VT)
TTL In (5VT)
TTL In (5VT)
TTL In (5VT)
TTL Out-OD
TTL Out-OD
TTL In (5VT)
TTL In-ST (5VT)
TTL In (5VT)
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-TS
CMOS I/O-OD
CMOS I/O-OD
CMOS Output
CMOS Input
CMOS Input
CMOS Input
R
Y
Type
6+2
I
4
N
Ports 10Mb Ethernet Access Controller
12 mA
12 mA
12 mA
12 mA
F
I
16mA
16mA
16mA
12mA
12mA
12mA
OL
Max
4mA
4mA
/ I
O
OH
R
Name and Functions
Management Bus – Data Bit [15:0]
Management Bus – Address Bit [11:1]
Management Bus – Address Strobe
Management Bus – Read/Write Control
Management Bus – Data Ready
Management Bus – 16 bit Data Bus
Management Bus – Chip Select
Management Bus – Interrupt Request
Management Bus – Master Reset
Management Bus – Bus Clock
XpressFlow Bus – Data Bit [31:27] or Manage-
ment Bus Interface Configuration bit [0:4]
XpressFlow Bus – Data Bit [26:0]
XpressFlow Bus – Message Envelope
XpressFlow Bus – End of Frame
XpressFlow Bus – Initiator Ready
XpressFlow Bus – Target Abort
XpressFlow Bus – High Priority Request
XpressFlow Bus – Bus Request to SC201
XpressFlow Bus – Bus Grant from SC201
XpressFlow Bus – Bus Overload
XpressFlow Bus – Clock
M
A
T
I
O
N
Rev. 2.1- February,
EA218