MEA-208 Zarlink Semiconductor, Inc., MEA-208 Datasheet - Page 10

• Manufacturer Part Number: MEA-208
• Description: 6+2 Ports Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2020 Series –
Ethernet Switch Chipset
2.2 Processor Bus Interface
t Supports various industry standard micro-processors including:
t Easily adapts to other industry standard CPUs
t Provides separate Address and Data bus
t Supports Big & Little Endian byte ordering
2.2.1 Pin Description
© 1998 Vertex Networks, Inc.
1999
Intel 186, 386, and 486 family or equivalent
Motorola MPC series embedded processors
P_C[4:0]
P_A[11:1]
P_D[15:0]
P_ADS#
P_RWC
P_RDY#
P_BS16#
P_CS#
P_INT
P_RST#
P_CLK
Symbol
P
•
R
CMOS Input
TTL In (5VT)
TTL I/O-TS (5VT) Data Bus Bit [15:0] – a 16-bit synchronous data bus.
TTL In (5VT)
TTL Input (5VT)
TTL Out-OD
TTL Out-OD
TTL Input (5VT)
CMOS Output
TTL In-ST (5VT) CPU Reset – Synchronous reset Input from Switch Manager CPU
TTL In (5VT)
E
Type
L
I
M
Processor Configuration bit [4:0]: – During the Reset Cycle, the P_C[4:0] pins provides the
processor configuration. By using external weak pull-up or -down resistors, they define the Ex-
ternal Management Bus Interface Configuration. These inputs are sampled at the trailing edge of
the Reset cycle.
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Address Bus Bit [11:1] – I/O port address
Address Strobe – indicates valid address is on the bus
Read/Write Control – indicates the current bus cycle is a read or write cycle. C[1] defines the
polarity of this signal during the Reset cycle.
Data Ready – timing indicates for bus data valid
Bus Size 16 – response to bus master that the EA208 only supports 16-bit data bus width.
Chip Select – indicates the XpressFlow Engine is the target for the current bus operation.
Interrupt Request to Switch Manager CPU The polarity of this signal output is programmable
via chip configuration register.
CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
Name and Functions
I
Lo
Hi
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU Bus interface, and
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid. If C[4] is High,
C[1]=Low
C[1]=High
N
CPU Clock
A
the P_D[15:0] are valid along in the same clock period as P_RDY is asserted. If C[4]
is Low, the P_RDY is asserted one clock period early ahead of the P_D[15:0] are
valid.
the setting of this bit is ignored.
1X Clock
2x Clock
C[0]
R
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
Y
6+2
I
Little Endian
10
Byte Order
Big Endian
N
t Supports 16-bit Data Bus
t Supports early RDY cycle
t Supports 1X or 2X CPU Clock
t Provides a single interrupt signal to Switch Manager CPU
Ports 10Mb Ethernet Access Controller
C[1]
F
Meets timing requirement for Intel/AMD 186 family proc-
essors
2X CPU Clock for 386 family processors
O
R
P_R/W#
P_W/R#
RWC
M
C[2]
A
T
Bus Size
I
C[3]
n/a
n/a
O
N
Rev. 2.1- February,
RDY Timing
Normal
Early
C[4]
EA218