MEA-224 Zarlink Semiconductor, Inc., MEA-224 Datasheet

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MEA-224

Manufacturer Part Number
MEA-224
Description
4-Port, Layer 2 Fast Ethernet Access Controller
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
EA-224
(XpressFlow
1. DISTINCTIVE
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©
1997
4 independent 10/100Mbps Ethernet Access Ports
State of the art 0.5 micron 3.3Volt CMOS process
352-PIN BGA package
Operating frequency
32-bit Local Buffer Memory Interface
Hardware assisted Buffer and Queue Management
to minimized CPU overhead
16-bit Processor Bus I/O Interface
32-bit XpressFlow Bus Interface
Supports unicast, multicast, and broadcast frames
Works together with SC-201 XpressFlow Engine
Supports both Half & Full Duplex operation
Programmable Flow Control Enable
CHARACTERISTICS
Direct interface with 10BaseT transceiver
IEEE 802.3u compliant MII (Media Independent In-
terface) and Serial Management interface
Direct interface with 100BaseTX, -T2, -T4, or -TF
physical transceivers
-33
-40
-50
Supports 128k to 1M bytes
Utilize high performance 32-bit Synchronous
Burst SRAM
Allows host to access Control Registers & Local
Buffer Memory
Supports Big and Little Endian CPUs
Direct interface with various different standard
microprocessors including 386, 486 families and
Motorola MPC series embedded processors.
Uses Granule for frame transferring between
Access Controllers
Also detects IEEE 802.3X MAC Control frames
Capable to forward frames at full line-rate
Distributed Flow Caching™ to reduce frame for-
warding latency
Jam Fake Collision for Half Duplex Mode
Transmit Flow Control Frame for IEEE 802.3x
Full Duplex Mode
(57(; (7:25.6
33 MHz maximum
40 MHz maximum
50 MHz maximum
– 4-Port Fast Ethernet Access Controller
T M
2001 Series 10/100 Ethernet Switch Chipset)
P R E L I M I N A R Y
Page: 1
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Three frame forwarding modes
Multi-Media ready with QoS supports
Complies with IEEE 802.1 Bridge Standard
VLAN ID Tagging & Stripping
Automatic retry frame transmission
Automatic receive filtering for bad frames for Store
& Forward Mode
Automatic statistic collection for RMON
Store-&-Forward
Safe Cut-Thru (Runt Free)
Turbo Cut-Thru (10Mbps Mode only)
Automatically selects the optimized mode for
forwarding
Allows manual frame forwarding mode selection
override
Four frame transmission priority queues
Assigns one unique MAC Address for each port
Auto padding if necessary after stripping
Transmit collision
Transmit buffer under-run
Bad FCS
Short events or frames under 64 bytes
Long events or frames over 1518 bytes
MEMORY
BUFFER
LOCAL
32
Port
0
10/100M BaseTx Ports
Access Controller
10/100M BaseTx Xceiver
4-Port Ethernet
D A T A
Management BUS
XpressFlow BUS
16
Port
Rev. 4.0 –December, 1997
EA-224
1
Port
2
32
Port
3
S H E E T

Related parts for MEA-224

MEA-224 Summary of contents

Page 1

EA-224 – 4-Port Fast Ethernet Access Controller T M (XpressFlow 2001 Series 10/100 Ethernet Switch Chipset) 1. DISTINCTIVE CHARACTERISTICS  4 independent 10/100Mbps Ethernet Access Ports Direct interface with 10BaseT transceiver IEEE 802.3u compliant MII (Media Independent In- terface) and ...

Page 2

XpressFlow-2001 Series – Ethernet Switch Chip-set 2. GENERAL DESCRIPTION: The EA-224 provides four 10/100Mbps Ethernet network ac- cess interface ports. MII interface is used to connect external PHY devices ...

Page 3

XpressFlow-2001 Series – Ethernet Switch Chip-set 3. PIN ASSIGNMENT 3.1 Logic Symbol L_D[31:0] L_A[18:2] 4 L_BWE[3:0]# 4 L_WE[3:0]# 4 L_OE[3:0 ...

Page 4

XpressFlow-2001 Series – Ethernet Switch Chip-set 3.2 Pin Assignment (Preliminary) Note: # Active low signal Input Input signal I-ST Input signal with Schmitt-Trigger Output Output signal (Tri-State driver) Out-OD ...

Page 5

XpressFlow-2001 Series – Ethernet Switch Chip-set Pin No(s). Symbol Control Buffer Memory Interface M4,N2,L3,M1,M2,L1,K3, L_D[31:0] L2,K4,K1,J3,K2,J1,J2, H3,H1,H2,G3,G1,G2,F1, F3,F2,E1,E3,E2,D1,D3, D2,C1,C2,B1 A6,B6,C8,A7,D8,D7,C9, L_A[18:2] A8,B8,A9,C10,B9,D10, A10,C11,B10,A11 C7 L_A[19] / L_OE[3]# D5,A5,A3 L_OE[2:0]# ...

Page 6

XpressFlow-2001 Series – Ethernet Switch Chip-set Pin No(s). Symbol Power Pins D6,D11,D16,D21,F4, VDD F23,L4,L23,T4,T23,AA4, AA23,AC6,AC11,AC16, AC21 A1,A2,A26,B2,B25,B26, VSS C3,C24,D4,D9,D14,D19, D23,H4,J23,N4,P23,V4, W23,AC4,AC8,AC13, AC18,AC23,AD3,AD24, AE1,AE2,AE25,AF1, AF25 (57(; (7:25.6 © 1997 D ...

Page 7

XpressFlow-2001 Series – Ethernet Switch Chip-set 3.3 Pin Reference Table: (352 pin BGA) Pin # Signal Name Pin # Signal Name F26 P_A[1] D17 S_D[11] G24 P_A[2] A17 S_D[12] ...

Page 8

XpressFlow-2001 Series – Ethernet Switch Chip-set 4. FUNCTIONAL DESCRIPTION 4.1 Local Memory (Local Buffer Memory) Interface  Use industry standard Synchronous Burst Mode SRAM bytes 32k ...

Page 9

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.1.2 Supported Memory Configurations RAM Chip # of RAM Total Buffer L_WE[3]# Size Chips Memory Size 32k 128k bytes 2 ...

Page 10

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.2 Management Bus Interface  Supports various industry standard micro- processors including: Intel 186, 386, and 486 family or equivalent Motorola MPC series ...

Page 11

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.2.2 Motorola MPC801 Processor Interface P_CLK {CLKOUT} P_ADS# {TS#} P_A[11:1] {A[20:30]} P_CS# P_RWC {RD/WR#} P_RDY# {TA#} P_D[15:0] (in) {D[0:15]} P_D[15:0] (out) {D[0:15]} Note: ...

Page 12

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.2.4 Intel 386 Processor Interface P_CLK PH2 (internal) PH2 P_ADS# P_A[11:1] P_CS# P_W/R# P_RDY# P_D[15:0] (in) P_D15:0] (out) Typical 386 CPU I/O Access ...

Page 13

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.2.5 Register Map Note: All 32-bit registers are D-word aligned. All 16-bit registers are also D-word aligned and right justified. For the Little ...

Page 14

XpressFlow-2001 Series – Ethernet Switch Chip-set Register Description Access Control Function (Chip Level controls) AVXR VLAN Control Table (VCT) Index Register AVDR VCT Data Register AVTC VLAN Type Code ...

Page 15

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.3 XpressFlow Bus Operation  Vertex’s optimized XpressFlow Bus architec- ture  Provides up to 1.6G bps switching bandwidth -33 1.07G bps -40 ...

Page 16

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.3.2 Bus Cycle Waveforms S_CLK S_MSGEN# S_D[31:0] C0 S_EOF# S_IRDY XpressFlow Bus Data Transfer Cycle S_CLK S_MSGEN# S_D[31:0] C0 S_EOF# S_TABT# Command Cycle ...

Page 17

XpressFlow-2001 Series – Ethernet Switch Chip-set S_CLK S_MSGEN# S_REQ[j]# S_GNT[j]# S_HPREQ# S_REQ[I]# S_GNT[I]# S_CLK S_REQ[k]# S_OVLD# Bus Overload pre-empts the data transfer request (57(; (7:25.6 © 1997 D A ...

Page 18

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.4 MII Interface  Fully compliant with IEEE 802.3u Media Inde- pendent Interface for connecting with external 10/100M Ethernet Physical Layer Transceiver  ...

Page 19

XpressFlow-2001 Series – Ethernet Switch Chip-set 40 nsec TXC TXEN TXD[3:0] 40 nsec 40 nsec RXC RXDV RXD[3:0] (57(; (7:25.6 © 1997 4-Port 10/100M Ethernet ...

Page 20

XpressFlow-2001 Series – Ethernet Switch Chip-set 4.4.2 PIN Mapping between MII Interface and 10Mbps Serial Interface MII Interface Symbol Type Mm_RXD[3:1] TTL In (5VT) Mm_RXD[0] TTL In Tm_RXD (5VT) ...

Page 21

XpressFlow-2001 Series – Ethernet Switch Chip-set 5. DC SPECIFICATION 5.1 ABSOLUTE MAXIMUM RATINGS Storage Temperature Operating Temperature Supply Voltage V with Respect Voltage on 5V Tolerant ...

Page 22

XpressFlow-2001 Series – Ethernet Switch Chip-set 6. AC SPECIFICATION 6.1 XpressFlow Bus Interface: S_CLK S17 S_D[31:0] S19 S_MSGEN# S21 S_EOF# S23 S_IRDY S27 S_TABT# S29 S_HPREQ# S31 S_GNT# S33 ...

Page 23

XpressFlow-2001 Series – Ethernet Switch Chip-set Symbol Parameter S1 S_D[31:0] output valid delay S2 S_MSGEN# output valid delay S3 S_EOF# output valid delay S4 S_IRDY output valid delay S6 ...

Page 24

XpressFlow-2001 Series – Ethernet Switch Chip-set 6.2 CPU Bus Interface: P_CLK P15 P16-min P_D[31:0] CPU Bus Interface – Output float delay timing P_CLK P16-max P16-min P_D[15:0] P17-max P17-min P_RDY# ...

Page 25

XpressFlow-2001 Series – Ethernet Switch Chip-set 6.3 Local Memory Interface: L_CLK L1 L2 L_D[31:0] Local Memory Interface – Input setup and hold timing L_CLK L10 L3-min L_D[31:0] Local Memory ...

Page 26

XpressFlow-2001 Series – Ethernet Switch Chip-set 7. PACKAGING INFORMATION 352-PIN BGA (35x35x2.33mm) Pin 1 I. 24.00 Ref 32.00 Ref 35.00 +/- 0.20 1.17 Ref 0.56 2.33 Ref ...

Page 27

... North America - East Coast Asia/Pacific 2 C Patent rights to use these components TECHNICAL DOCUMENTATION - NOT FOR RESALE Tel: (978) 322-4800 Fax: (978) 322-4888 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 2 C System, provided that the system conforms ...

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