MEA-208 Zarlink Semiconductor, Inc., MEA-208 Datasheet - Page 15

• Manufacturer Part Number: MEA-208
• Description: 6+2 Ports Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2020 Series –
Ethernet Switch Chipset
2.3 XpressFlow Bus Operation
t Vertex Networks’ optimized XpressFlow Bus architecture
t Provides 1.6G bps switching bandwidth
t Full multi bus master structure
t Allows XpressFlow Engine to communicate with Access Con-
2.3.1 Pin Description
© 1998 Vertex Networks, Inc.
1999
trollers via a message passing protocol
-33
-40
-50
S_D[31:0]
S_MSGEN#
S_EOF#
S_IRDY
S_TABT#
S_HPREQ#
S_REQ#
S_GNT#
S_OVLD#
S_CLK
Symbol
P
1.07G bps
1.28G bps
1.6G bps
R
E
CMOS In-
L
I/O-OD
I/O-OD
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
I/O-TS
CMOS
CMOS
CMOS
Output
CMOS
Output
CMOS
Type
Input
put
I
M
Name and Functions
Data Bus Bit [31:0] – a 32-bit synchronous data bus.
Note:
Configuration bit [0:3]
Message Envelope – encompasses the entire period of a message transfer. Targets use the
leading edge of this signal to detect the beginning of a message transfer, and to decode the
message header for the intended target(s).
End of Frame – only used by frame data transfer messages to identify the end of frame condi-
tion. This signal is synchronous with the Rx Frame Status word appended to the end of the
message.
Initiator Ready – a normal true signal. When negated, it indicates the initiator had asserted wait
state(s) in between command words. Target should use this signal as enable signal for latching
the data from the bus.
Target Abort – when asserted, the target had aborted the reception of current message on the
bus.
High Priority Request – indicates one or more Bus Requester is requesting for high priority
message transfer.
Bus Request –Bus Request signals from Access Controller to Bus Access Arbitrator in Xpress-
Flow Engine
Bus Grant –Bus Grant signals from Bus Arbitrator to Bus Requester
Bus Overload – when asserted, all data forwarding bus bandwidth has been allocated. Cannot
support additional load for data forwarding traffic.
XpressFlow Bus Clock – 33MHz system clock
I
N
A
During the system RESET period, Data Bit [31:28] are used as Processor Interface
R
Y
6+2
I
15
t Built-in intelligent bus load regulator for data traffic balancing
t Provides centralized bus arbitration with two level request pri-
N
Ports 10Mb Ethernet Access Controller
orities
F
Command Messages for passing control information be-
tween devices
Data Messages for forwarding an Ethernet frame from re-
ceiving port to transmission port
High priority for Data Messages
Low priority for Command Messages
O
R
M
A
T
I
O
N
Rev. 2.1- February,
EA218