74AUP2G125DC,125 NXP Semiconductors, 74AUP2G125DC,125 Datasheet - Page 11

IC BUFF DVR 3-ST DL L PWR 8VSSOP

74AUP2G125DC,125

Manufacturer Part Number
74AUP2G125DC,125
Description
IC BUFF DVR 3-ST DL L PWR 8VSSOP
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP2G125DC,125

Package / Case
US8, 8-VSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
0.5 uA
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
19 ns @ 1.1 V to 1.3 V or 10.8 ns @ 1.4 V to 1.6 V or 8.4 ns @ 1.65 V to 1.95 V or 6.3 ns @ 2.3 V to 2.7 V or 5.8 ns @ 3 V to 3.6 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP2G125DC-G
74AUP2G125DC-G
935280727125
NXP Semiconductors
Table 8.
Voltages are referenced to GND (ground = 0 V); for test circuit see
[1]
[2]
[3]
[4]
[5]
74AUP2G125
Product data sheet
Symbol Parameter
t
C
C
dis
L
PD
= 5 pF, 10 pF, 15 pF and 30 pF
All typical values are measured at nominal V
t
t
t
C
P
f
f
C
V
N = number of inputs switching;
Σ(C
pd
en
dis
i
o
D
CC
PD
= input frequency in MHz;
L
= output frequency in MHz;
is the same as t
is the same as t
= output load capacitance in pF;
= C
is the same as t
L
is used to determine the dynamic power dissipation (P
= supply voltage in V;
× V
disable time
power dissipation
capacitance
PD
Dynamic characteristics
CC
× V
2
× f
CC
o
2
) = sum of the outputs.
× f
PLH
PZH
PHZ
i
× N + Σ(C
and t
and t
and t
PHL
PZL
PLZ
Conditions
nOE to nY; see
output enabled; f
V
L
.
.
I
.
V
V
V
V
V
V
V
V
V
V
V
V
× V
= GND to V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
= 0.8 V
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
= 0.8 V
= 1.1 V to 1.3 V
= 1.4 V to 1.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3.0 V to 3.6 V
2
…continued
× f
o
All information provided in this document is subject to legal disclaimers.
) where:
CC
CC
.
Figure 9
i
= 1 MHz;
Rev. 7 — 21 September 2010
D
in μW).
[4]
[5]
Min
Figure
6.0
4.4
5.1
3.6
5.2
-
-
-
-
-
-
-
10.
Typ
25 °C
49.9
Low-power dual buffer/line driver; 3-state
9.9
7.7
8.7
6.2
8.7
2.7
2.8
2.9
3.0
3.6
4.2
[1]
Max
13.3
11.1
10.5
9.6
7.6
-
-
-
-
-
-
-
Min
4.8
3.1
2.8
2.6
2.6
-
-
-
-
-
-
-
74AUP2G125
−40 °C to +125 °C
(85 °C)
Max
14.8
10.8
12.4
10.8
8.6
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
(125 °C)
Max
16.5
12.1
13.8
13.1
9.6
-
-
-
-
-
-
-
11 of 24
Unit
ns
ns
ns
ns
ns
ns
pF
pF
pF
pF
pF
pF

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