74aup2g125gt NXP Semiconductors, 74aup2g125gt Datasheet
74aup2g125gt
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74aup2g125gt Summary of contents
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Low-power dual buffer/line driver; 3-state Rev. 02 — 19 April 2007 1. General description The 74AUP2G125 provides the dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level ...
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... Ordering information Type number Package Temperature range Name 74AUP2G125DC +125 C 74AUP2G125GT +125 C 74AUP2G125GM +125 C 4. Marking Table 2. Marking Type number 74AUP2G125DC 74AUP2G125GT 74AUP2G125GM 5. Functional diagram 1OE 2OE Fig 1. Logic symbol 74AUP2G125_2 Product data sheet Description VSSOP8 plastic very thin shrink small outline package ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 3. Pin configuration SOT765-1 (VSSOP8) 74AUP2G125 1OE GND 4 Transparent top view Fig 4. Pin configuration SOT833-1 (XSON8) 6.2 Pin description Table 3. Pin description Symbol Pin SOT765-1 and SOT833-1 1OE GND ...
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... NXP Semiconductors 7. Functional description [1] Table 4. Function table Input nOE [ HIGH voltage level LOW voltage level Don’t care high-impedance OFF-state. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). ...
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... NXP Semiconductors 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current CC C input capacitance I C output capacitance +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off OFF leakage current I supply current CC I additional supply current +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional power-off OFF leakage current I supply current CC I additional supply current CC [1] One input at V 0.6 V, other input [2] To show I remains very low when the input-disable feature is enabled. ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay nA to nY; see pd t enable time nOE to nY; see en t disable time nOE to nY; see dis propagation delay nA to nY; see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t disable time nOE to nY; see dis propagation delay nA to nY; see pd t enable time nOE to nY; see en t disable time nOE to nY; see ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation output enabled capacitance V = GND [1] All typical values are measured at nominal V ...
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... NXP Semiconductors nOE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and V are typical output voltage drop that occur with the output load Fig 7. Enable and disable times Table 10. Measurement points ...
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... NXP Semiconductors Test data is given in Table 11. Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Load circuitry for switching times Table 11 ...
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... NXP Semiconductors 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2 pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0. 0.12 0.00 0.60 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 0.15 1.55 OUTLINE VERSION IEC SOT902 Fig 11 ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date 74AUP2G125_2 20070419 • ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 14 Abbreviations ...