74ALVC162839T Fairchild Semiconductor, 74ALVC162839T Datasheet
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74ALVC162839T
Specifications of 74ALVC162839T
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74ALVC162839T Summary of contents
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... CMOS power dissipation. Ordering Code: Order Number Package Number 74ALVC162839T MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...
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Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table Inputs I CLK REGE Logic HIGH L Logic LOW X Don’t Care, ...
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Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) (Note 3) 0. Input Diode Current ( Output Diode Current (I ) ...
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AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX Propagation Delay PHL PLH Bus-to-Bus (REGE Propagation Delay PHL PLH Clock to Bus (REGE Propagation Delay PHL PLH REGE ...
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AC Loading and Waveforms FIGURE 1. AC Test Circuit (Input Characteristics 1MHz; t Symbol 3.3V 0. FIGURE 2. Waveform ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...