DM74AS374 Fairchild Semiconductor, DM74AS374 Datasheet

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DM74AS374

Manufacturer Part Number
DM74AS374
Description
Manufacturer
Fairchild Semiconductor
Datasheet

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DM74AS374N
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© 2000 Fairchild Semiconductor Corporation
DM74AS374WM
DM74AS374N
DM74AS374
Octal D-Type Edge-Triggered Flip-Flops
with 3-STATE Outputs
General Description
These 8-bit registers feature totem-pole 3-STATE outputs
designed specifically for driving highly-capacitive or rela-
tively low-impedance loads. The high-impedance state and
increased high-logic-level drive provide these registers with
the capability of being connected directly to and driving the
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
The eight flip-flops of the AS374 are edge-triggered D-type
flip-flops. On the positive transition of the clock, the Q out-
puts will be set to the logic states that were set up at the D
inputs.
A buffered output control input can be used to place the
eight outputs in either a normal logic state (HIGH or LOW
logic levels) or a high impedance state. In the high-imped-
ance state the outputs neither load nor drive the bus lines
significantly.
The output control does not affect the internal operation of
the flip-flops. That is, the old data can be retained or new
data can be entered even while the outputs are off.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Package Number
M20B
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DS006310
Features
Switching specifications at 50 pF
Switching specifications guaranteed over full tempera-
ture and V
Advanced oxide-isolated, ion-implanted Schottky TTL
process
Functionally and pin-for-pin compatible with LS and ALS
TTL counterparts
Improved AC performance over LS and ALS TTL coun-
terparts
3-STATE buffer-type outputs drive bus lines directly
Package Description
CC
range
October 1986
Revised March 2000
www.fairchildsemi.com

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DM74AS374 Summary of contents

Page 1

... Package Number DM74AS374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74AS374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Function Table Output Clock D Control LOW State H HIGH State X Don’t Care Positive Edge Transition Z High Impedance State Q Previous Condition www.fairchildsemi.com Logic ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Voltage Applied to Disabled Output Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V High Level Input Voltage ...

Page 4

Switching Characteristics over recommended operating free air temperature range Symbol Parameter f Maximum Clock Frequency V MAX CC t Propagation Delay Time R PLH L LOW-to-HIGH Level Output Propagation Delay Time PHL HIGH-to-LOW Level Output t Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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