FAN3121T Fairchild Semiconductor, FAN3121T Datasheet - Page 2

• Manufacturer Part Number: FAN3121T
• Description: The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
Ordering Information
FAN3121CMPX
FAN3121CMX
FAN3121TMPX
FAN3121TMX
FAN3122CMPX
FAN3122CMX
FAN3122TMPX
FAN3122TMX
Package Outlines
Thermal Characteristics
8-Lead 3x3mm Molded Leadless Package (MLP)
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1.
2.
3.
4.
5.
6.
Part Number
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Estimates derived from thermal simulation; actual values depend on the application.
Theta_JL (Θ
(including any thermal pad) that are typically soldered to a PCB.
Theta_JT (Θ
assuming it is held at a uniform temperature by a top-side heatsink.
Theta_JA (Θ
and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards
JESD51-2, JESD51-5, and JESD51-7, as appropriate.
Psi_JB (Ψ
temperature and an application circuit board reference point for the thermal environment defined in Note 4. For
the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and
protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB
copper adjacent to pin 6.
Psi_JT (Ψ
temperature and the center of the top of the package for the thermal environment defined in Note 4.
Figure 3.
JT
JB
): Thermal characterization parameter providing correlation between the semiconductor junction
): Thermal characterization parameter providing correlation between semiconductor junction
JL
JT
JA
Inverting Channels +
Enable
Non-Inverting Channels +
Enable
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
3x3mm MLP-8 (Top View)
): Thermal resistance between the semiconductor junction and the top surface of the package,
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
Package
Logic
(1)
Threshold
CMOS
CMOS
Input
TTL
TTL
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
3x3mm MLP-8
SOIC-8
Θ
2
Package
1.2
38
JL
(2)
Figure 4.
Θ
JT
64
29
(3)
Status
Θ
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
RoHS
SOIC-8 (Top View)
JA
42
87
Eco
(4)
Ψ
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
Tape & Reel
2.8
41
JB
Packing
Method
(5)
Ψ
0.7
2.3
JT
(6)
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Quantity
per Reel
3,000
2,500
3,000
2,500
3,000
2,500
3,000
2,500
Units
°C/W
°C/W