FDMF6823B Fairchild Semiconductor, FDMF6823B Datasheet - Page 13

• Manufacturer Part Number: FDMF6823B
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6823B • Rev. 1.0.2
Adaptive Gate Drive Circuit
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shoot-
through (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 27
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
VSWH
VSWH
PWM
GH
GL
to
Notes:
t
t
PWM
t
t
t
SMOD#
t
t
PD_xxx
D_xxx
PD_PHGLL
PD_PLGHL
PD_PHGHH
PD_SLGLL
PD_SHGLH
V
IH_PWM
= delay from IC generated signal to IC generated signal.
= propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
= SMOD# fall to LS V
= PWM rise to LS V
= PWM fall to HS V
= SMOD# rise to LS V
CCM
t
= PWM rise to HS V
PD_PHGLL
t
D_DEADON
1.0V
90%
t
PD_PLGHL
GS
GS
GS
GS
fall, V
fall, V
GS
rise, V
fall, V
V
rise, V
t
IL_PWM
D_DEADOFF
IH_PWM
IL_PWM
IL_SMOD
IH_PWM
t
IH_SMOD
2.2V
R_GL
to 90% HS V
to 90% LS V
to 90% LS V
to 10% HS V
10%
to 10% LS V
Figure 27.
GS
GS
GS
GS
GS
t
(SMOD# held LOW)
D_HOLD-OFF
3-state
Enter
Example (t
t
F_GL
DCM
V
PWM and 3-StateTiming Diagram
D_DEADON
IH_PWM
3-state
Exit
t
t
R_GH
– LS V
PD_TSGHH
GS
13
(GL) LOW to HS V
Exiting 3-state
t
t
Dead Times
t
t
PD_TSGHH
PD_TSGLH
D_DEADON
D_DEADOFF
HIGH, Q2 begins to turn off after a propagation delay
(t
Q1 begins to turn on after adaptive delay t
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (t
GH-to-PHASE falls below 2.2V, Q2 begins to turn on
after adaptive delay t
PD_PHGLL
t
Example (t
V
D_HOLD-OFF
TRI_HI
3-state
= PWM 3-state to LOW to LS V
= PWM 3-state to HIGH to HS V
= LS V
Enter
= VSWH fall to LS V
t
F_GH
GS
GS
PD_PHGLL
). Once the GL pin is discharged below 1.0V,
fall to HS V
(GH) HIGH)
DCM
– PWM going HIGH to LS V
V
IH_PWM
GS
GS
t
rise, LS-comp trip value (~1.0V GL) to 10% HS V
3-state
rise, SW-comp trip value (~2.2V VSWH) to 10% LS V
PD_TSGHH
Exit
PD_PLGHL
D_DEADOFF
GS
GS
rise, V
rise, V
IL_PWM
). Once the voltage across
IH_PWM
GS
.
(GL) going LOW)
to 10% LS V
to 10% HS V
t
D_HOLD-OFF
3-state
Enter
GS
GS
D_DEADON
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t
3-state
PD_TSGLH
Exit
GS
V
V
V
V
IH_PWM
TRI_HI
TRI_LO
IL_PWM
GS
V
V
90%
10%
.
10%
90%
OUT
IN