FSEZ1307 Fairchild Semiconductor, FSEZ1307 Datasheet - Page 12

• Manufacturer Part Number: FSEZ1307
• Description: This third-generation Primary Side Regulation (PSR) PWM controller combination power MOSFET, FSEZ1307, provides several features to enhance the performance of low-power flyback converters
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FSEZ1307 • Rev. 1.0.2
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 5V, respectively. During startup, the hold-up
capacitor must be charged to 16V through the startup
resistor to enable the FSEZ1307. The hold-up capacitor
continues to supply V
from the auxiliary winding of the main transformer. V
is not allowed to drop below 5V during this startup
process. This UVLO hysteresis window ensures that
hold-up capacitor properly supplies V
Protections
The FSEZ1307 has several self-protection functions,
such
Temperature Protection (OTP), and pulse-by-pulse
current limit. All the protections are implemented as
auto-restart mode. Once the abnormal condition occurs,
the switching is terminated and the MOSFET remains
off, causing V
turn-off voltage of 5V, the internal startup circuit is
enabled again and the supply current drawn from the
HV pin charges the hold-up capacitor. When V
reaches the turn-on voltage of 16V, normal operation
resumes. In this manner, the auto-restart alternately
enables and disables the switching of the MOSFET until
the abnormal condition is eliminated (see Figure 29).
V
V
voltage conditions. If the V
open-loop feedback condition, OVP is triggered and the
PWM switching is disabled. The OVP has a debounce
time (typically 200µs) to prevent false triggering due to
switching noises.
DD
DD
Over-Voltage Protection (OVP)
over-voltage protection prevents damage from over-
as
Figure 29. Auto-Restart Operation
Over-Voltage
DD
to drop. When V
DD
until power can be delivered
Protection
DD
voltage exceeds 24V at
DD
DD
drops to the V
during startup.
(OVP),
Over-
DD
DD
DD
12
Over-Temperature Protection (OTP)
The built-in temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C.
Pulse-by-Pulse Current Limit
When the sensing voltage across the current-sense
resistor exceeds the internal threshold of 0.8V, the
MOSFET is turned off for the remainder of switching
cycle. In normal operation, the pulse-by-pulse current
limit is not triggered since the peak current is limited by
the control loop.
Leading-Edge Blanking (LEB)
Each time the power MOSFET switches on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period,
the current-limit comparator is disabled and cannot
switch off the gate driver. As a result, conventional RC
filtering can be omitted.
Gate Output
The FSEZ1307 output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
15V Zener diode to protect the power MOSFET
transistors against undesired over-voltage gate signals.
Built-In Slope Compensation
The sensed voltage across the current-sense resistor is
used for current mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability and prevents sub-harmonic oscillations due to
peak-current mode control. The FSEZ1307 has a
synchronized, positive-slope ramp built-in at each
switching cycle.
Noise Immunity
Noise from the current sense or the control signal can
cause
continuous-conduction
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FSEZ1307, and
increasing the power MOS gate resistance are advised.
significant
pulsewidth
mode.
jitter,
While
particularly
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slope
in