FAN6753 Fairchild Semiconductor, FAN6753 Datasheet
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FAN6753
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FAN6753 Summary of contents
Page 1
... With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. To further reduce power consumption, FAN6753 is manufactured using the BiCMOS process, which allows an operating current of only 2.7mA. FAN6753 integrates a full-range frequency-hopping function internally that helps reduce EMI emission of a power supply with minimum line filters ...
Page 2
... NC No connection For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors. © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M:SOP) ...
Page 3
... Application Diagram Internal Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 Figure 3. Typical Application Figure 4. Functional Block Diagram 3 www.fairchildsemi.com ...
Page 4
... All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 Parameter (1, 2) <50°C) A Human Body Model, ...
Page 5
... OSC t Hopping Period Green-Mode Frequency OSC-G f Frequency Variation vs Frequency Variation vs. Temperature f DT Deviation PWM Frequency f OSC f OSC-G © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 Conditions V – 0.16V DD-ON V =15V, GATE Open DD V +0.1V TH-OLP V =90V (V =120V =0V DD HV=500V +1V ...
Page 6
... When activated, the output is disabled and the latch is turned off. 4. The threshold temperature for enabling the output again and resetting the latch, after over-temperature protection has been activated. © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 (Continued) Conditions V > 5.2V, after LATCHth 100µ ...
Page 7
... Figure 10. Supply Current Drawn from HV Pin (I vs. Temperature -40 -30 - Temperature (℃) Figure 12. Frequency in Normal Mode (f vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0 100 125 -40 Figure 7. Operation Supply Current (I ) vs. Temperature DD-ST 12 ...
Page 8
... Temperature (℃) Figure 18. V Over-Voltage Protection (V DD vs. Temperature © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0 ℃ 75 ℃ 85 ℃ 100 ℃ 125 ℃ -40 ℃ ) Figure 15. Delay Time of FB Pin Open-Loop ...
Page 9
... External Latch Function (LATCH Pin) The LATCH pin can be used to control the FAN6753 entering latch mode by pulling this pin over 5.2V for 100µs. If floating, the LATCH pin is internally pulled HIGH to 3.5V not recommended to float or short the LATCH pin to GND ...
Page 10
... Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN6753, and increasing the is charged up to the DD power MOS gate resistance also improve performance. ...
Page 11
... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 5.00 4.80 A 3.81 ...
Page 12
... Fairchild Semiconductor Corporation FAN6753 • Rev. 1.0.3 12 www.fairchildsemi.com ...