FAN6755W Fairchild Semiconductor, FAN6755W Datasheet - Page 12

• Manufacturer Part Number: FAN6755W
• Description: This highly integrated PWM controller provides several features to enhance the performance of flyback converters
• Manufacturer: Fairchild Semiconductor

© 2009 Fairchild Semiconductor Corporation
FAN6755W / FAN6755UW • Rev. 1.0.5
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
(1N4007 / 100KΩ recommended) or bulk capacitor
through a resistor, R
HV (typically 3.5mA) charges the hold-up capacitor
through the diode and resistor. When the V
level reaches V
this moment, the V
FAN6755W/UW to maintain V
winding of the main transformer to provide the operating
current.
Operating Current
Operating current is around 2mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides an off-
time modulation to reduce the switching frequency in
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. V
derived from the voltage feedback loop, is taken as the
reference. Once V
switching frequency is continuously decreased to the
minimum green-mode frequency of around 23KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and V
When the voltage on the SENSE pin reaches around
V
immediately. V
voltage around 0.83V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 7.8V in normal mode. During startup, the hold-
up capacitor must be charged to 16V through the startup
resistor to enable the IC. The hold-up capacitor
continues to supply V
delivered from auxiliary winding of the main transformer.
V
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply V
COMP
DD
must not drop below 7.8V during startup. This
=(V
FB
–0.6)/4,
COMP
DD-ON
DD
FB
hold-up capacitance.
, the startup current switches off. At
is internally clamped to a variable
is lower than the threshold voltage,
HV
a
DD
. Startup current drawn from pin
DD
switch
capacitor only supplies the
before the energy can be
FB
, the feedback voltage.
DD
DD
cycle
before the auxiliary
during startup.
is
DD
FB
terminated
, which is
capacitor
12
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5.5ms soft-start
circuit significantly reduces the startup current spike and
output voltage overshoot.
Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability
FAN6755W/UW inserts a synchronized positive-going
ramp at every switching cycle.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher V
V
high-line input voltage equal to that at low-line input. The
value of R-C network should not be so large that it
affects the power limit (shown in Figure 21). R and C
should be less than 100 and 470pF, respectively.
IN
increases, making the maximum output power at
IN
and
voltage. The threshold voltage decreases as
Figure 21.
prevents
Current-Sense R-C Filter
sub-harmonic
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oscillation.