FAN6756 Fairchild Semiconductor, FAN6756 Datasheet - Page 13

• Manufacturer Part Number: FAN6756
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FAN6756 • Rev. 1.0.4
V
V
V
voltage exceeding the IC voltage rating. When the V
voltage exceeds 24.5V, the protection is triggered. This
protection is typically caused by an open circuit in the
secondary-side feedback network.
Over-Temperature Protection (OTP) and External
Latch Triggering
The RT pin provides adjustable Over-Temperature
Protection (OTP) and external latch triggering function.
For OTP, an NTC thermistor, R
a resistor R
ground. The internal current source, I
introduces voltage on RT as:
At high ambient temperature, R
V
than t
FAN6756 enters Latch Mode protection.
The OTP can be trigged by pulling down the RT pin
voltage using an opto-coupler or transistor. Once V
less than V
the protection is triggered and FAN6756 enters Latch
Mode protection.
When OTP is not used, it is recommended to place a
100kΩ resistor between this pin and ground to prevent
noise interference.
Open-Loop/Overload Protection (OLP)
Because of the pulse-by-pulse current limit capability,
the maximum peak current is limited, and therefore the
maximum input power is also limited. If the output
consumes more than this limited maximum power, the
output voltage (V
the currents through the opto-coupler and transistor
become virtually zero and V
is higher than V
(57.5ms), OLP is triggered. OLP is also triggered when
the feedback loop is open by soldering defect.
Sense Short-Circuit Protection (SSCP)
FAN6756 provides safety protection for Limited Power
Source (LPS) test. When the current-sense resistor is
short circuited by a soldering defect during production,
the current sensing information is not properly obtained,
resulting in unstable operation of power supply.
To protect the power supply against a short circuit across
the current-sense resistor, FAN6756 shuts down when
current sense voltage is very low; even with a relatively
large duty cycle. As shown in Figure 31, the current-
sense voltage is sampled t
turn-on. If the sampled voltage (V
for 11 consecutive switching cycles (170µs), the
FAN6756 shuts down immediately. V
with line voltage. At 122V DC input, it is typically 50mV
(V
RT
DD
DD
RT
SSCP-L

. When V
Over-Voltage Protection (OVP)
I
over-voltage protection prevents IC damage from
RT
D-OTP1

); at 366V DC, it is typically 100mV (V
(
R
NTC
RTTH2
A
RT
(14.5ms), the protection is triggered and

, is connected between the RT pin and
R
A
is lower than V
)
(0.7V) for longer than t
O
FB-OLP
) drops below the set voltage. Then,
(4.6V) for longer than t
ON-SSCP
FB
is pulled HIGH. Once V
NTC
RTTH1
NTC
S-CS
(4.55µs) after the gate
, usually in series with
decreases, reducing
) is lower than V
(1.035V) for longer
SSCP
D-OTP2
varies linearly
RT
SSCP-H
(100µA),
(185µs),
).
(5)
D-OLP
RT
SSCP
DD
FB
is
13
Two-Level Under-Voltage Lockout (UVLO)
As shown in Figure 32, as long as protection is not
triggered, the turn-off threshold of V
at V
level to terminate PWM gate switching is changed to
V
below V
operating current from V
down the discharge of V
This delays re-startup after shutdown by protection to
minimize the input power and voltage/current stress of
switching devices during a fault condition.
Gate Output / Soft Driving
The BiCMOS output stage has a fast totem-pole gate
driver. The output driver is clamped by an internal 14.5V
Zener diode to protect the power MOSFET gate from
over voltage. A soft driving is implemented to minimize
Electromagnetic Interference (EMI) by reducing the
switching noise.
GATE
V
V
V
GATE
DD-OFF
V
DD-OFF
DD-ON
DD-OLP
V
RESTART
V
V
DD-ON
UVLO
UVLO
V
DD
DD
Figure 33. V
(11V), as shown in Figure 33. When V
Figure 32. V
DD-OFF
(6.5V). When a protection is triggered, the V
Figure 31. Timing Diagram of SSCP
, the switching is terminated and the
DD
DD
UVLO at Protection Mode
UVLO at Normal Mode
DD
17V
17V
6.5V
11V
DD
5V
7V
is reduced to I
until V
DD
DD
is fixed internally
reaches V
DD-OLP
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DD
to slow
DD-OLP
drops
t
t
DD
.