TMPM380FWDFG Toshiba, TMPM380FWDFG Datasheet - Page 401

• Manufacturer Part Number: TMPM380FWDFG
• Manufacturer: Toshiba

Specifications of TMPM380FWDFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 100
• Package: QFP(14×20)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
Protocol
Select the 9-bit UART mode for the master and slave controllers.
Set SC0MOD <WU> to “1” for the slave controllers to make them ready to receive data.
The master controller is to transmit a single frame of data that includes the slave controller
select code (8 bits). In this, the most significant bit (bit 8) <TB8> must be set to “1”.
Each slave controller receives the above data frame; if the code received matches with the
controller's own select code, it clears the WU bit to “0”.
The master controller transmits data to the designated slave controller (the controller of
which SC0MOD <WU> bit is cleared to “0”). In this, the most significant bit (bit 8) <TB8>
must be set to “0”.
The slave controllers with the <WU> bit set to “1” ignore the receive data because the most
significant bit (bit 8) <RB8> is set to “0” and thus no interrupt (INTRX0) is generated.
Also, the slave controller with the <WU> bit set to “0” can transmit data to the master
controller to inform that the data has been successfully received.
An example: Using the internal clock f
serially linked as follows.
start
start
TXD
Master
bit 0
bit 0
RXD
1
1
Slave controller select code
2
2
TMPM380/M382 - 52 / 52 -
3
3
Data
TXD
4
4
Select code
00000001
Slave 1
SYS
5
5
RXD
as the transfer clock, two slave controllers are
6
6
7
7
TXD
Select code
00001010
bit 8
Slave 2
“1”
“0”
8
RXD
stop
stop
TMPM380/M382