TMPM380FWDFG Toshiba, TMPM380FWDFG Datasheet - Page 375

• Manufacturer Part Number: TMPM380FWDFG
• Manufacturer: Toshiba

Specifications of TMPM380FWDFG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 128K
• Rom Type: Flash
• Ram (kbytes): 12K
• Number Of Pins: 100
• Package: QFP(14×20)
• Vcc: 5V
• Cpu Mhz: 40
• Ssp (ch) Spi: 2
• I2c/sio (ch): 2
• Uart/sio (ch): 5
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: N
• Cs/wait Controller (ch): -
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: -
• 12-bit Ad Converter: 18
• 16-bit Timer / Counter: 8
• Motor / Igbt Control: Y
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Clock Gear: Y
• Low-power Hold Function: -
• Remote Control Interface: Y
• Hardware Cec Controller: -
• Comparators: -
• Low-voltage Detector: Y
• Etm Hardware Trace: 2-bit

13 Serial channel (UART/SIO)
Receive Side
Transmit Side
Receive Side
Transmit Side
I/O interface mode:
UART Mode:
13.3.21 Signal Generation Timing
Interrupt generation
timing
Framing error
generation timing
Parity error generation
timing
Overrun error
generation timing
Interrupt generation
timing
Interrupt generation
timing
Interrupt generation timing
Interrupt generation timing
Overrun error generation
timing
Interrupt generation timing
Interrupt generation timing
Under-run error generation
timing
(<WBUF> = 0)
(<WBUF> = 1)
(<WBUF> = 0)
(<WBUF> = 1)
(<WBUF> = 0)
(<WBUF> = 1)
(Note 1) Do not modify any control register when data is being sent or received (in a
(Note 2) Do not stop the receive operation (by setting SC0MOD0 <RXE> = “0”) when
(Note 3) Do not stop the transmit operation (by setting SC0MOD1 <TXE> = “0”)
Mode
Mode
state ready to transmit or receive).
data is being received.
when data is being transmitted.
Around the center of
the 1st stop bit
Around the center of
the stop bit
⎯
Around the center of
the stop bit
Just before the stop bit
is sent
Immediately after data
is moved to transmit
shift register (just
before start bit
transmission)
SCLK output mode Immediately after the rising edge of the last SCLK
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
SCLK output mode Immediately after the rising edge of the last SCLK (just after data
SCLK input mode Immediately after the rising edge or falling edge of the last SCLK (right
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
SCLK output mode Immediately after the rising edge of the last SCLK
SCLK input mode Immediately after the rising or falling edge of the last SCLK (for rising or
SCLK output mode Immediately after the rising edge of the last SCLK or just after data is
SCLK input mode Immediately after the rising or falling edge of the last SCLK or just after
SCLK input mode Immediately after the falling or rising edge of the next SCLK
9-bit
9-bit
TMPM380/M382 - 26 / 52 -
Around the center of the 1st
stop bit
Around the center of the stop
bit
Around the center of the last
(parity) bit
Around the center of the stop
bit
Just before the stop bit is sent Just before the stop bit is sent
Immediately after data is
moved to transmit shift
register (just before start bit
transmission).
falling edge mode, respectively).
transfer to receive buffer) or just after receive buffer is read.
after data is moved to receive buffer).
falling edge mode, respectively)
falling edge mode, respectively)
moved to Transmit shift register
data is moved to Transmit shift register
8-bit with parity
8-bit with parity
Around the center of the 1st stop bit
Around the center of the stop bit
Around the center of the last (parity) bit
Around the center of the stop bit
Immediately after data is moved to transmit
shift register (just before start bit transmission)
8-bit, 7-bit, and 7-bit with parity
8-bit, 7-bit, and 7-bit with parity
TMPM380/M382