FMS6501MSA28X Fairchild Semiconductor, FMS6501MSA28X Datasheet - Page 5

• Manufacturer Part Number: FMS6501MSA28X
• Description: IC VIDEO SW MATRIX 12X9 28SSOP
• Manufacturer: Fairchild Semiconductor
• Type: Video Switch, 12-Input 9-Outputr

Specifications of FMS6501MSA28X

• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FMS6501MSA28XTR; FMS6501MSA28X_NL; FMS6501MSA28X_NLTR; FMS6501MSA28X_NLTR

© 2004 Fairchild Semiconductor Corporation
FMS6501 Rev. 1.0.4
Digital Interface
The I
enables, input to output routing, input clamp / bias, and
output gain. The I
(0000 0110) with the ability to offset it to 0x86 (1000
0110) by tying the ADDR pin high.
Both data and address data, of eight bits each, are writ-
ten to the I
There are separate internal addresses for each output.
Each output’s address includes bits to select an input
channel, adjust the output gain, and enable or disable
the output amplifier. More than one output can select the
Output Control Register Contents and Defaults
Notes:
1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power
2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately
Output Control Register MAP
Notes:
1. IN4 is provided for forward compatibility and should always be written as ‘0’ in the FMS6501.
Clamp Control Register Contents and Defaults
Clamp Control Register Map
Control Name
Register Name
Register
Control Name
Name
down also de-selects any input routed to the specified output.
300mV with the 6dB gain setting.
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
CLAMP1
CLAMP2
2
Enable
C-compatible interface is used to program output
Gain
Clmp
Inx
2
C address to access all the control functions.
Register
Address
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
2
C address of the FMS6501 is 0x06
Width
2 bits
5 bits
Register
Address
1 bit
Width
0x1D
0x1E
1 bit
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Bit 7
Type
Write
Write
Write
Resv’d
Clmp8
Bit 7
Type
Write
Default
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Gain1
Bit 6
0
0
0
Resv’d
Clmp7
Bit 6
Default
0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Gain0
Bit(s)
Bit5
6:5
4:0
7
Resv’d
Clmp6
Bit5
5
same input channel for one-to-many routing. When the
outputs are disabled, they are placed in a high-imped-
ance state. This allows multiple FMS6501 devices to be
paralleled to create a larger switch matrix. Typical output
power-up time is less than 500ns.
The clamp / bias control bits are written to their own
internal address, since they should always remain the
same regardless of signal routing. They are set based on
the input signal connected to the FMS6501.
All undefined addresses may be written without effect.
Bit(s)
Channel Enable: 1=Enable, 0=Power Down
Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB
Input selected to drive this output: 00000=OFF
00001=IN1, 00010=IN2... 01100=IN12
7:0
Bit4
IN4
IN4
IN4
IN4
IN4
IN4
IN4
IN4
IN4
Resv’d
Clmp5
Bit4
(1)
Clamp / Bias selection: 1 = Clamp, 0 = Bias
Bit3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
IN3
Clmp12
Clmp4
Bit3
Description
Bit2
Description
Clmp11
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
Clmp3
Bit2
Clmp10
Bit1
Clmp2
IN1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
IN1
Bit1
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(1)
(2)
Clmp1
Clmp9
Bit0
Bit0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
IN0
,