DS80CH11 Maxim, DS80CH11 Datasheet - Page 57

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

PMDIN1; SFR ADDR.=0BEH
PMDIN2; SFR ADDR.=0F6H
Read/Write Access: Read only.
Initialization: Undefined on any type of reset
Each input data register (KBDIN, PMDIN1 or PMDIN2)
is a read–only register to the SEM and a write–only reg-
ister to the host. The associated input buffer full flag
(KIBF, PIBF1 or PIBF2) will be set when the host CPU
writes to one of the input buffers. The SEM can enable
an “input buffer full” interrupt on any port by setting the
associated interrupt enable bit (EKB, EPB1 or EPB2).
9.4 KBSTAT / PMSTAT1/PMSTAT2 – STATUS REGISTERS
KBSTAT; SFR ADDR.=0ADH
PMSTAT1; SFR ADDR.=0BDH
PMSTAT2; SFR ADDR.=0F5H
Read/Write Access: Unrestricted.
Initialization: XXXXXX00B on any type of reset
The operation of the bits in the status registers of both
ports are summarized below:
P1ST7
P2ST7
BIT 7
BIT 7
BIT 7
KST7
BIT 7
BIT 7
P1ST6
P2ST6
BIT 6
BIT 6
BIT 6
KST6
BIT 6
BIT 6
P1ST5
P2ST5
KST5
BIT 5
BIT 5
BIT 5
BIT 5
BIT 5
P1ST4
P2ST4
KST4
BIT 4
BIT 4
BIT 4
BIT 4
BIT 4
Upon interrupt, the SEM’s firmware should check to see
if the incoming byte is a command or data by reading the
command/data flag, i.e., KC/D, PC/D1 or PC/D2, in the
status register followed by a read of the input data regis-
ter. The contents of the input data registers are unaf-
fected by any type of reset.
PC/D1
PC/D2
BIT 3
BIT 3
BIT 3
BIT 3
BIT 3
KC/D
P1ST2
P2ST2
BIT 2
BIT 2
BIT 2
KST2
BIT 2
BIT 2
PIBF1
PIBF2
BIT 1
BIT 1
BIT 1
BIT 1
BIT 1
KIBF
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POBF1
POBF2
KOBF
BIT 0
BIT 0
BIT 0
BIT 0
BIT 0
DS80CH11