DS80CH11 Maxim, DS80CH11 Datasheet - Page 40

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

MASTER RECEIVE OPERATION TIMING Figure 6–5
In response to RXIx being set on the next to the last data
byte, the ANAKx bit can be set so that a negative
acknowledge bit is returned to the slave when the last
data byte is received. This action signals the slave to
stop transmitting bytes and return to receive mode. If
there is only one byte to be received from the slave
device, the ANAKx bit can be set at the time the slave
address is transmitted so that the negative acknowl-
edge signal will be transmitted after the reception of the
single byte.
When the last data byte is received and RXIx cleared,
the STOP condition can be issued by setting the STOx
bit to a 1. ANAKx can be returned to a 0 at this time to
return a positive acknowledge on future received bytes
(e.g., received slave address). After the STOP condi-
tion is sent the STOx bit will be automatically cleared
and X/Rx will remain at 0, indicating the port hardware is
still in receive mode.
DS80CH11
011200 40/88
SDAx/SCLx
ACKSx BIT
ANAKx BIT
TSTAx BIT
STOx BIT
STAx BIT
DATA BUF:
X/Rx BIT
RXIx BIT
TXIx BIT
WRITE
READ
Ç Ç
Ç Ç Ç Ç
É É É É
É É É É
É É É É
(Sr)
S
SLAVE ADDR.
Ç Ç
Ç Ç Ç Ç
Ç Ç
Ç Ç Ç Ç
R/W
1
Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
A
DATA
Arbitration with another master may be lost during the
transmission of the slave address as described above in
the Master Transmit mode. Once receive operation is in
progress in the Master Receive mode, then arbitration
loss can only occur while a negative acknowledge is
being returned on the bus. In this case arbitration is lost
when another master on the bus pulls this signal low.
Since this occurs at the end of a serial byte, no further
clock pulses are generated. The ARLx flag will be set to
signal this event.
6.3.3
Figure 6–6 illustrates the timing for Slave Receive
operation. In this mode another master transfers one or
more bytes to the SEM which is addressed as a slave
device.
When the 2–Wire ports are initialized following a reset,
the SEM’s 7–bit slave addresses are established by
Ç Ç
Ç Ç Ç Ç
A
Ç Ç
Ç Ç Ç Ç
Slave Receive
DATA
Ç Ç
Ç Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
A
DATA
Ç Ç
Ç Ç Ç Ç
A
Ç Ç
Ç Ç Ç Ç
P