DS80CH11 Maxim, DS80CH11 Datasheet - Page 46

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

SAR A/D SIMPLIFIED BLOCK DIAGRAM Figure 7–2
7.5 CONVERSION TIME
An internal clock signal called ACLK is used to clock the
successive approximation logic in performing the A/D
conversion. ACLK is derived from the microcontroller
clock signal through divide–down logic. A total of 16
clock cycles are required to perform the conversion.
The minimum ACLK period is 1 s, a faster clock can
result in erroneous results. At the other extreme, the
maximum clock period is 6.25
nature of the internal sample–hold circuitry.
In order to meet these requirements and accommodate
a wide range of CPU clock frequencies a programmable
prescaler is provided to generate appropriate converter
clock (ACLK) from the CPU clock.
Based on the micro’s CPU clock, the ACLK frequency
can be set to one of 16 values via the four A/D clock
prescaler (APS) bits in the ADCON2 register. This
results in a conversion clock frequency as given by the
formula below:
DS80CH11
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t
ACLK
= t
MCLK
ACLK
START
EOC
ANALOG IN
REFHI
REFLO
(N+1)
s due the dynamic
CONTROL
LOGIC
RESOLUTION
ZRO (SAMPLE)
CVT
2
D/A CONVERTER
OFFSET
SAMPLING
APPROXIMATION
10–BIT
SUCCESSIVE
where t
machine clock period, and N is the clock prescale value
ranging from 0 to 15 as programmed in the APS bits.
The CPU machine clock period is the oscillator clock
period (t
mined by the programming of the system clock divider
bits (CD1, CD0) in the PMR register.
The resulting t
Table 7–1 gives a set of conversion times at usable A/D
clock prescaler settings for a range of microcontroller
clock frequencies, assuming that the microcontroller
machine clock is at its default value of 4 crystal clock
periods.
REGISTER
SAR [9..0]
ACLK
CLK
1.00 s < t
) multiplied times 4, 64, or 1024 as deter-
is the analog clock period, t
ACLK
–
COMP
+
must meet the criteria of
ACLK
< 6.25 s
MCLK
is the CPU