DS80CH11 Maxim, DS80CH11 Datasheet - Page 33

• Manufacturer Part Number: DS80CH11
• Description: The system energy manager is a highly integrated microcontroller that provides several key features for systems including key scanning and control, battery and power management, as well as two 2-Wire serial I/O Ports
• Manufacturer: Maxim

6.0 2–WIRE SERIAL INTERFACE
6.1 INTRODUCTION
The SEM provides two industry standard 2–Wire serial
interfaces for processor–processor and processor–
slave bi–directional communication. The major fea-
tures of these buses include:
2–WIRE SERIAL PORT BLOCK DIAGRAM Figure 6–1
Only two signal lines are required per bus: a serial
clock line (SCL) and a serial data line (SDA).
Each device connected to the bus is software
addressable by a unique address.
Masters can operate as Master–transmitter or Mas-
ter–receiver.
Multiple master capability via collision detection and
arbitration to prevent data corruption if two or more
masters simultaneously initiate a data transfer.
8 PRESCALE
DIVIDE BY
t
MCLK
0DAH
09AH
09DH
0D9H
09CH
0D3H
R/W
R/W
R/W
EN
EN
EN
2WSADRx – ADDRESS
2WFSx – FREQUENCY
2WCONx – CONTROL
RELOAD VALUE
REGISTER
REGISTER
DIVIDE BY
COMPARE
ADDRESS
SELECT
INTERNAL
DATA BUS
0DAH
0DBH
09EH
09BH
0D2H
09BH
0D2H
09FH
R/W
WR
RD
RD
CONTROL
TIMING &
LOGIC
Both on–chip 2–Wire ports support four modes of
operation: Master transmitter, Master receiver, Slave
transmitter, Slave receiver. Byte–oriented data trans-
port, clock generation, address recognition, and bus
control arbitration are all performed by the hardware.
Double–buffering is provided on receive, allowing a full
word time to service the port during multiple byte data
transfers.
Figure 6–1 is a block diagram which illustrates the hard-
ware of both 2–Wire serial ports. For simplicity “x” rep-
resents 1 for Port 1 and 2 for Port 2.
MSB
EN
EN
Serial clock synchronization allows devices with dif-
ferent bit rates to communicate via the same serial
bus.
Devices can be added to or removed from the bus
without affecting any other circuit on the bus.
EN
DOUT
EN
2WSTAT1x – STATUS
2WSTAT2x – STATUS
2WDATx – RECEIVE
DATA BUFFER
REGISTER
REGISTER
REGISTER
SHIFT
ARBITRATION
CLOCK GEN.
SERIAL
LOGIC
LSB
DIN
ACK
011200 33/88
DS80CH11
SDAx
SCLx
PIN
PIN