ST72334J4 STMicroelectronics, ST72334J4 Datasheet - Page 61

• Manufacturer Part Number: ST72334J4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334J4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OC i HR reg-
2. If the OC i E bit is not set, the OCMP i pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 37. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OC i LR register is also written.
general I/O port and the OLVL i bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMP i are set while the counter value equals
the OC i R register value (see
62). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
external clock mode, OCF i and OCMP i are set
while the counter value equals the OC i R regis-
ter value plus 1 (see
for generating external events on the OCMP i
pins even if the input capture mode is also
used.
OLV i bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
Figure 39 on page
CPU
i
R register and the
CPU
Figure 38 on page
/4, f
/2, OCF i and
OC1E
CPU
OCIE
OC2E
OCF1
/8 or in
62).
FOLV2 FOLV1
Forced Compare Output capability
When the FOLV i bit is set by software, the OLVL i
bit is copied to the OCMP i pin. The OLV i bit has to
be toggled in order to toggle the OCMP i pin when
it is enabled (OC i E bit=1). The OCF i bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVL i bits have no effect in either One-Pulse
mode or PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
ST72334J/N, ST72314J/N, ST72124J
CC0
0
0
OLVL1
0
Latch
Latch
1
2
OCMP2
OCMP1
Pin
Pin
61/153