ST72334J4 STMicroelectronics, ST72334J4 Datasheet - Page 19

• Manufacturer Part Number: ST72334J4
• Description: 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,ADC, 16-BIT TIMERS, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72334J4

• Clock Sources: crystal/ceramic resonator oscillators or RC oscillators, external clock, backup Clock Security System
• 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Two 16-bit Timers With: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes

DATA EEPROM (Cont’d)
6.3 MEMORY ACCESS
The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in
access modes.
Read Operation (LAT=0)
The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.
Write Operation (LAT=1)
To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.
Figure 8. Data EEPROM Programming Flowchart
Figure 8
describes these different memory
IN EEPROM AREA
READ MODE
READ BYTES
INTERRUPT GENERATION
CLEARED BY HARDWARE
PGM=0
LAT=0
IF IE=1
(with the same 11 MSB of the address)
When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.
At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.
Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
It is not possible to read the latched data.
This note is ilustrated by the
START PROGRAMMING CYCLE
WRITE UP TO 16 BYTES
PGM=1 (set by software)
ST72334J/N, ST72314J/N, ST72124J
0
IN EEPROM AREA
WRITE MODE
PGM=0
LAT=1
LAT=1
LAT
1
Figure
9.
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