ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 53

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

MISCELLANEOUS REGISTERS (Cont’d)
MISCELLANEOUS REGISTER 2 (MISCR2)
Reset Value: 0000 0000 (00h)
Bits 7:5 = Reserved.
Bits 4:0 = P[4:0] Power Management Bits
These bits are set and cleared by software. They
can be used to switch the on-chip peripherals of
the microcontroller ON or OFF. The registers are
not changed by switching the peripheral OFF and
then ON (contents are frozen while OFF).
0: Peripheral ON (running)
1: Peripheral OFF
MISCELLANEOUS REGISTER 3 (MISCR3)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = WDGHALT Watchdog and HALT Mode
This bit is set and cleared by software. It deter-
mines if a RESET is generated when entering Halt
mode while the Watchdog is active (WDGA bit =1
in the WDGCR register).
Table 16. Miscellaneous Register Map and Reset Values
HALT
WDG
Address
7
0
7
(Hex.)
Bit
P0
P1
P2
P3
P4
4A
4C
49
0
0
MISCR1
Reset Value
MISCR2
Reset Value
MISCR3
Reset Value
Register
Label
0
0
P4
0
WDGHALT
Peripheral
IS31
P3
IS11
Timer
PWM
USB
DTC
7
I2C
0
0
0
0
IS30 PWM1 PWM0
P2
IS10
P1
6
0
0
0
0
0
Doc ID 7215 Rev 4
P0
0
0
MCO
5
0
0
0
0
0
In either case, the Watchdog will not reset the
MCU if a HALT instruction is executed while the
USB is in Suspend mode.
0: If the Watchdog is active, it will reset the MCU if
1: When a HALT instruction is executed, the MCU
Bits 6:4 = Reserved, forced by hardware to 0.
Bits 3:2= IS3[1:0] ei2 Interrupt sensitivity
Interrupt sensitivity, defined using the IS3[1:0] bits,
is applied to the ei2 interrupts (Port C):
These 2 bits must be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bit 1 = PWM1 PWM1 Output Control
0: PWM1 Output alternate function disabled (I/O
1: PWM1 Output alternate function enabled
Bit 0 = PWM0 PWM0 Output Control
0: Output alternate function disabled (I/O pin free
1: PWM0 Output alternate function enabled
IS31 IS30
a HALT instruction is executed (unless the USB
is in Suspend mode)
will enter Halt mode (without generating a reset)
even if the Watchdog is active.
0
0
1
1
pin free for general purpose I/O).
for general purpose I/O).
IS21
P4
4
0
0
0
0
0
1
0
1
IS20
IS31
P3
3
0
0
0
External Interrupt Sensitivity
Falling edge & low level
Rising and falling edge
Falling edge only
Rising edge only
IS30
CP1
P2
2
0
0
0
PWM1
CP0
P1
ST72651AR6
1
0
0
0
PWM0
CPEN
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P0
0
0
0
0
1