ST72651AR6 STMicroelectronics, ST72651AR6 Datasheet - Page 28

• Manufacturer Part Number: ST72651AR6
• Description: LOW-POWER, FULL-SPEED USB 8-BIT MCU WITH 32K FLASH, 5K RAM, FLASH CARD I/F, TIMER, PWM, ADC, I2C, SPI
• Manufacturer: STMicroelectronics

Specifications of ST72651AR6

• Dual Supply Management: analog voltage detector on the USB power line to enable smart power switching from USB power to battery (on E suffix devices).
• Programmable Internal Voltage Regulator For Memory Cards (2.8v To 3.5v) Supplying: Flash Card I/O lines (voltage shifting)
• 5 Usb Endpoints: 1 control endpoint
• Dtc (data Transfer Coprocessor): Universal Serial/Parallel communications interface, with software plug-ins for current and future protocol standards

ST72651AR6
RESET SEQUENCE MANAGER (Cont’d)
6.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
If the external RESET pulse is shorter than
t
signal on the RESET pin will be stretched. Other-
wise the delay will not be applied (see long ext.
Reset in
Figure 18. Reset Block Diagram
28/161
1
w(RSTL)out
RESET
Figure
(see short ext. Reset in
17).
ON
V
weak pull-up resistor.
DD
R
ON
Figure
h(RSTL)in
17), the
Doc ID 7215 Rev 4
f
CPU
in
GENERATOR
PULSE
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
6.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■
■
The device RESET pin acts as an output that is
pulled low when V
V
The LVD filters spikes on V
to avoid parasitic resets.
6.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t
DD
Power-On RESET
Voltage Drop RESET
<V
IT-
(falling edge) as shown in
w(RSTL)out
WATCHDOG RESET
LVD RESET
DD
<V
DD
IT+
w(RSTL)out
.
shorter than t
(rising edge) or
INTERNAL
RESET
Figure
.
Figure
17.
g(VDD)
17.