ST72260G1 STMicroelectronics, ST72260G1 Datasheet - Page 66

• Manufacturer Part Number: ST72260G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72260G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

ST72260Gx, ST72262Gx, ST72264Gx
16-BIT TIMER (Cont’d)
11.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are loaded in
their respective shadow registers (double buffer)
only at the end of the PWM period (OC2) to avoid
spikes on the PWM output pin (OCMP1). The
shadow registers contain the reference values for
comparison in PWM “double buffering” mode.
Note: There is a locking mechanism for transfer-
ring the OCiR value to the buffer. After a write to
the OCiHR register, transfer of the new compare
value to the buffer is inhibited until OCiLR is also
written.
Unlike in Output Compare mode, the compare
function is always enabled in PWM mode.
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
2. Load the OC1R register with the value corre-
3. Select the following in the CR1 register:
4. Select the following in the CR2 register:
66/172
sponding to the period of the signal using the
formula in the opposite column.
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
– Using the OLVL1 bit, select the level to be ap-
– Using the OLVL2 bit, select the level to be ap-
– Set OC1E bit: the OCMP1 pin is then dedicat-
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see
plied to the OCMP1 pin after a successful
comparison with OC1R register.
plied to the OCMP1 pin after a successful
comparison with OC2R register.
ed to the output compare 1 function.
Table 14
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
ing application can be calculated using the follow-
ing formula:
Where:
t
f
PRESC
If the timer clock is an external clock the formula is:
Where:
t
f
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See
Notes:
1. The OCF1 and OCF2 bits cannot be set by
2. The ICF1 bit is set by hardware when the coun-
CPU
EXT
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
Clock Control
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
= Timer prescaler factor (2, 4 or 8 depend-
i
R register value required for a specific tim-
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
Counter
= OC1R
OCiR Value =
Counter
= OC2R
When
When
ing on CC[1:0] bits, see
Control
OCiR =
Bits)
Bits).
Pulse Width Modulation cycle
t
*
f
EXT
OCMP1 = OLVL2
PRESC
t
OCMP1 = OLVL1
Counter is reset
*
ICF1 bit is set
f
CPU
-5
to FFFCh
Figure
Table 14 Clock
- 5
45)