ST72260G1 STMicroelectronics, ST72260G1 Datasheet - Page 46

• Manufacturer Part Number: ST72260G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72260G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

ST72260Gx, ST72262Gx, ST72264Gx
MISCELLANEOUS REGISTERS (Cont’d)
10.3 MISCELLANEOUS REGISTER DESCRIPTION
MISCELLANEOUS REGISTER 1 (MISCR1)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts. These
two bits can be written only when the I[1:0] bits in
the CC register are set to 1 (interrupt masked).
ei1: Port B (C optional)
Bit 5 = MCO Main clock out selection
This bit enables the MCO alternate function on the
PC2 I/O port. It is set and cleared by software.
0: MCO alternate function disabled (I/O pin free for
1: MCO alternate function enabled (f
Bits 4:3 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts. These
two bits can be written only when the I[1:0] bits in-
the CC register are set to 1 (interrupt masked).
ei0: Port A (C optional)
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Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
Falling edge & low level
Rising edge only
Falling edge only
Rising and falling edge
IS11
general-purpose I/O)
port)
7
External Interrupt Sensitivity
External Interrupt Sensitivity
IS10 MCO IS01
IS00
CP1
CPU
CP0
IS11 IS10
IS01 IS00
on I/O
0
1
0
1
0
0
1
1
SMS
0
0
1
0
1
0
1
0
1
Bits 2:1 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is
applied in the various slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software
Bit 0 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. f
1: Slow mode. f
See low power consumption mode and MCC
chapters for more details.
f
CPU
in SLOW mode
f
f
f
f
OSC2
OSC2
OSC2
OSC2
/ 16
CPU
/ 2
/ 4
/ 8
CPU
is given by CP1, CP0
=
f
OSC2
CP1
0
1
0
1
CP0
0
0
1
1