ST72260G1 STMicroelectronics, ST72260G1 Datasheet - Page 123

• Manufacturer Part Number: ST72260G1
• Description: 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES
• Manufacturer: STMicroelectronics

Specifications of ST72260G1

• 4 K Or 8 Kbytes Program Memory: ROM or single voltage extended Flash (XFlash) with read-out protection, write protection, In-Circuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt,Wait and Slow
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes

INSTRUCTION SET OVERVIEW (Cont’d)
12.2 INSTRUCTION GROUPS
The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may
Using a pre-byte
The instructions are described with one to four op-
codes.
In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.
The whole instruction becomes:
to the number of bytes required to compute the ef-
fective address
These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:
Load and Transfer
Stack operation
Increment/Decrement
Compare and Tests
Logical operations
Bit Operation
Conditional Bit Test and Branch
Arithmetic operations
Shift and Rotates
Unconditional Jump or Call
Conditional Branch
Interruption management
Condition Code Flag modification
PC-2
PC-1
PC
PC+1
End of previous instruction
Prebyte
opcode
Additional word (0 to 2) according
LD
PUSH
INC
CP
AND
BSET
BTJT
ADC
SLL
JRA
JRxx
TRAP
SIM
CLR
POP
DEC
TNZ
OR
BRES
BTJF
ADD
SRL
JRT
WFI
RIM
be subdivided into 13 main groups as illustrated in
the following table:
using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.
rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.
direct indexed addressing mode by a Y one.
12.2.1 Illegal Opcode Reset
In order to provide enhanced robustness to the de-
vice against unexpected behaviour, a system of il-
legal opcode detection is implemented. If a code to
be executed does not correspond to any opcode
or prebyte value, a reset is generated. This, com-
bined with the Watchdog, allows the detection and
recovery from an unexpected fault or interference.
Note: A valid prebyte associated with a valid op-
code forming an unauthorized combination does
not generate a reset.
PDY 90
PIX 92
PIY 91
RSP
BCP
XOR
SUB
SRA
JRF
HALT
SCF
ST72260Gx, ST72262Gx, ST72264Gx
CPL
SBC
RLC
JP
IRET
RCF
Replace an X based instruction
Replace an instruction using di-
Replace an instruction using X in-
NEG
MUL
RRC
CALL
SWAP
CALLR
SLA
NOP
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RET