ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 267

• Manufacturer Part Number: ST72521R9-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST72521R9-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

ST72521xx-Auto
23
23.1
23.1.1
23.1.2
23.1.3
23.1.4
23.1.5
Known limitations
All Flash and ROM devices
External RC option
The external RC clock source option described in previous datasheet revisions is no longer
supported and has been removed from this specification.
Safe connection of OSC1/OSC2 pins
The OSC1 and/or OSC2 pins must not be left unconnected, otherwise the ST7 main
oscillator may start and, in this configuration, could generate an f
excess of the allowed maximum (> 16 MHz), putting the ST7 in an unsafe/undefined state.
Refer to
Reset pin protection with LVD enabled
As mentioned in
page
capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.
Unexpected reset fetch
If an interrupt request occurs while a “POP CC” instruction is executed, the interrupt
controller does not recognize the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a “POP CC” instruction must always be preceded by a “SIM” instruction.
External interrupt missed
To avoid any risk of generating a parasitic interrupt, the edge detector is automatically
disabled for one clock cycle during an access to either DDR and OR. Any input signal edge
during this period will not be detected and will not generate an interrupt.
This case can typically occur if the application refreshes the port configuration registers at
intervals during runtime.
Workaround
The workaround is based on software checking the level on the interrupt pin before and after
writing to the PxOR or PxDDR registers. If there is a level change (depending on the
sensitivity programmed for this pin) the interrupt routine is invoked using the call instruction
with three extra PUSH instructions before executing the interrupt routine (this is to make the
call compatible with the IRET instruction at the end of the interrupt service routine).
But detection of the level change does not make sure that edge occurs during the critical 1
cycle duration and the interrupt has been missed. This may lead to occurrence of same
interrupt twice (one hardware and another with software call).
241, when the LVD is enabled, it is recommended not to connect a pull-up resistor or
Section 6.4: Multi-oscillator (MO) on page
Note 2
below
Doc ID 17660 Rev 1
Figure 105: RESET pin protection when LVD is enabled on
41.
OSC
clock frequency in
Known limitations
267/276