ST72521R9-Auto STMicroelectronics, ST72521R9-Auto Datasheet - Page 124

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ST72521R9-Auto

Manufacturer Part Number
ST72521R9-Auto
Description
8-bit MCU for automotive
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72521R9-Auto

Hdflash Endurance
100 cycles, data retention 20 years
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt, Wait and Slow
Serial peripheral interface (SPI)
14
14.1
14.2
Note:
14.3
124/276
Serial peripheral interface (SPI)
Introduction
The Serial Peripheral Interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves
however the SPI interface cannot be a master in a multimaster system.
Main features
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
General description
Figure 55
registers:
The SPI is connected to external devices through four pins:
Full duplex synchronous transfers (on 3 lines)
Simplex synchronous transfers (on 2 lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun flags
SPI Control Register (SPICR)
SPI Control/Status Register (SPICSR)
SPI Data Register (SPIDR)
MISO (Master In / Slave Out data)
MOSI (Master Out / Slave In data)
SCK (Serial Clock out by SPI masters and input by SPI slaves)
SS (Slave select): This input signal acts as a ‘chip select’ to let the SPI master
communicate with slaves individually and to avoid contention on the data lines. Slave
SS inputs can be driven by standard I/O ports on the master MCU.
CPU
/2 max. slave mode frequency (see note)
shows the serial peripheral interface (SPI) block diagram. There are three
Doc ID 17660 Rev 1
CPU
/4 max.)
ST72521xx-Auto

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