ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 56

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ST72324BK2

Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72324BK2

Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
Power saving modes
56/193
Figure 28. Halt timing overview
Figure 29. Halt mode flowchart
1. WDGHALT is an option bit. See
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to
4. Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are
Table 25: Interrupt mapping
set to the current software priority level of the interrupt routine and recovered when the CC register is
popped.
[MCCSR.OIE = 0]
Run
instruction
for more details.
Halt
N
Section 14.1 on page 179
WDGHALT
(MCCSR.OIE = 0)
Watchdog
Halt
Halt instruction
reset
1
Interrupt
Y
(1)
256 or 4096 CPU
(3)
Enable
cycle delay
interrupt
Reset
0
256 or 4096 CPU clock
Oscillator
Peripherals
CPU
Oscillator
Peripherals
CPU
Oscillator
Peripherals
CPU
I[1:0] bits
I[1:0] bits
I[1:0] bits
N
or
Fetch reset vector
or service interrupt
cycle
for more details.
Y
Reset
Watchdog
(2)
delay
Disable
vector
Fetch
XX
XX
on
off
on
on
on
on
10
off
off
off
(4)
(4)
Run
ST72324Bxx

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