ST72324BK2 STMicroelectronics, ST72324BK2 Datasheet - Page 31
ST72324BK2
Manufacturer Part Number
ST72324BK2
Description
5V RANGE 8-BIT MCU WITH 8 TO 32K FLASH/ROM, 10-BIT ADC, 4 TIMERS, SPI, SCI INTERFACE
Manufacturer
STMicroelectronics
Datasheet
1.ST72324BJ6.pdf
(193 pages)
Specifications of ST72324BK2
Hdflash Endurance
1 kcycle at 55 °C, data retention 40 years at 85 °C
Clock Sources
crystal/ceramic resonator oscillators, int. RC osc. and ext. clock input
4 Power Saving Modes
Slow, Wait, Active-halt, and Halt
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ST72324Bxx
6
6.1
6.2
Caution:
Supply, reset and clock management
Introduction
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components. An overview is shown in
For more details, refer to dedicated parametric section.
Main features
●
●
●
●
PLL (phase locked loop)
If the clock frequency input to the PLL is in the range 2 to 4 MHz, the PLL can be used to
multiply the frequency by two to obtain an f
byte. If the PLL is disabled, then f
The PLL is not recommended for applications where timing accuracy is required.
Furthermore, it must not be used with the internal RC oscillator.
Figure 11. PLL block diagram
Optional Phase Locked Loop (PLL) for multiplying the frequency by 2 (not to be used
with internal RC oscillator in order to respect the max. operating frequency)
Multi-Oscillator clock management (MO)
–
–
Reset Sequence Manager (RSM)
System Integrity management (SI)
–
–
5 crystal/ceramic resonator oscillators
1 Internal RC oscillator
Main supply low voltage detection (LVD)
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply
f
OSC
OSC2
PLL x 2
Figure
= f
/ 2
OSC
OSC2
12.
/2.
of 4 to 8 MHz. The PLL is enabled by option
PLL option bit
Supply, reset and clock management
0
1
f
OSC2
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