ST7MC1K4 STMicroelectronics, ST7MC1K4 Datasheet - Page 259

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ST7MC1K4

Manufacturer Part Number
ST7MC1K4
Description
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7MC1K4

Hdflash Endurance
100 cycles, data retention
Clock Sources
crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
Four Power Saving Modes
Halt, Active-Halt, Wait and Slow
Main Clock Controller With
Real time base, Beep and Clock-out capabilities
Two 16-bit Timers With
2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
8-bit Pwm Auto-reload Timer With
2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

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CLOCK AND TIMING CHARACTERISTICS (Cont’d)
Figure 137. PLL And Clock Detector Signal Start Up Sequence
Notes:
1. Lock does not go low without resetting the PLLEN bit.
2. Before setting the CKSEL bit by software in order to switch to the PLL clock, a period of t
elapsed.
3. 2 clock cycles are missing after CKSEL = 1
4. CKSEL bit must be set before enabling the CSS interrupt (CSSIE=1).
CKSEL
OSCIN
PLLEN
(PLL and CKD)
PLL CLOCK
LOCK
f
CSSD
CSSIE
INTERRUPT
CLK
2)
4)
t
setup
t lock
OSCIN Clock
16Mhz
3)
PLL clock
f
VCO
t
hold
ST7MC1xx/ST7MC2xx
=
1)
6 Mhz
lock
must have
259/309

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