ST7MC1K4 STMicroelectronics, ST7MC1K4 Datasheet - Page 194

• Manufacturer Part Number: ST7MC1K4
• Description: 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,BRUSHLESS MOTOR CONTROL, 5 TIMERS, SPI, LINSCI(TM)
• Manufacturer: STMicroelectronics

Specifications of ST7MC1K4

• Hdflash Endurance: 100 cycles, data retention
• Clock Sources: crystal/ceramic resonator oscillators and by-pass for external clock, clock security system.
• Four Power Saving Modes: Halt, Active-Halt, Wait and Slow
• Main Clock Controller With: Real time base, Beep and Clock-out capabilities
• Two 16-bit Timers With: 2 input captures, 2 output compares, external clock input, PWM and pulse generator modes
• 8-bit Pwm Auto-reload Timer With: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.9.3 Dead Time Generator
When using typical triple half bridge topology for
power converters, precautions must be taken to
avoid short circuits in half bridges. This is ensured
by driving high and low side switches with comple-
mentary signals and by managing the time be-
tween the switching-off and the switching-on in-
stants of the adjacent switches.
This time is usually known as deadtime and has to
be adjusted depending on the devices connected
to the PWM outputs and their characteristics (in-
trinsic delays of level-shifters, delays due to power
switches,...).
When driving motors in six-step mode, the dead-
time generator function also allows synchronous
rectification to be performed on the switch adja-
cent to the one where PWM is applied to reduce
conduction losses.
Figure 111. Dead Time waveforms
Figure 112. Dead time waveform with delay greater than the negative PWM pulse
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1
Input signal
Reference
Output A
Output B
Output A
Output B
Input
Delay
For each of the three PWM channels, there is one
6-bit Dead Time generator available.
It generates two output signals: A and B.
The A output signal is the same as the input phase
signal except for the rising edge, which is delayed
relative to the input signal rising edge.
The B output signal is the opposite of the input
phase signal except the rising edge which is de-
layed relative to the input signal falling edge.
Figure 111
output signals of the deadtime register and its in-
puts.
If the delay is greater than the width of the active
phase (A or B) then the corresponding pulse is not
generated (see
Delay
shows the relationship between the
Figure 112
Delay
and
Figure
113).
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V