PSMN4R0-30YL NXP Semiconductors, PSMN4R0-30YL Datasheet

Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology

PSMN4R0-30YL

Manufacturer Part Number
PSMN4R0-30YL
Description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology
Manufacturer
NXP Semiconductors
Datasheet

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1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
Table 1.
Symbol
V
I
P
T
Static characteristics
R
Dynamic characteristics
Q
Q
Avalanche ruggedness
E
D
j
DS
tot
DS(AL)S
DSon
GD
G(tot)
PSMN4R0-30YL
N-channel 30 V 4 mΩ logic level MOSFET in LFPAK
Rev. 04 — 10 March 2011
High efficiency due to low switching
and conduction losses
Class-D amplifiers
DC-to-DC converters
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
gate-drain charge
total gate charge
non-repetitive
drain-source avalanche
energy
T
T
Conditions
T
see
V
T
V
V
see
V
I
R
D
j
mb
mb
j
GS
GS
DS
GS
GS
≥ 25 °C; T
= 25 °C
= 99 A; V
Figure 1
Figure 15
= 25 °C; V
= 25 °C; see
= 10 V; I
= 4.5 V; I
= 12 V; see
= 10 V; T
= 50 Ω; unclamped
sup
j
D
≤ 175 °C
D
j(init)
GS
= 15 A;
≤ 30 V;
= 10 A;
Suitable for logic level gate drive
sources
Motor control
Server power supplies
Figure
Figure 2
= 10 V;
= 25 °C;
14;
Min
-
-
-
-55
-
-
-
-
Product data sheet
Typ
-
-
-
-
2.72 4
4.3
17.6 -
-
Max Unit
30
100
69
175
-
41
V
A
W
°C
mΩ
nC
nC
mJ

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PSMN4R0-30YL Summary of contents

Page 1

... PSMN4R0-30YL N-channel mΩ logic level MOSFET in LFPAK Rev. 04 — 10 March 2011 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for use in industrial and communications applications. ...

Page 2

... T pulsed ° j(init) ≤ Ω; unclamped V sup GS All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Graphic symbol mbb076 Version Min Max - 30 ≤ 160 nJ DS(AL kΩ ...

Page 3

... P (%) 150 200 T (°C) mb Fig DSon All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL 120 der 100 Normalized total power dissipation as a function of mounting base temperature 10 μs 100 μ 100 ms ...

Page 4

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN4R0-30YL Product data sheet N-channel mΩ logic level MOSFET in LFPAK Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Min Typ Max - 1 1.82 003aac648 t p δ ...

Page 5

... Figure MHz °C; see Figure 0.5 Ω 4.7 Ω R G(ext) All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Min Typ Max = 25 ° -55 ° 1.3 1.7 2.15 0. 2.45 - ...

Page 6

... A/µ 003aac639 25 ° (V) GS Fig 6. 003aac642 4 100 I (A) D Fig 8. All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Min Typ = 25 ° 120 (A) V (V) = 3.2 GS 4.5 100 ...

Page 7

... GS Fig 10. Drain-source on-state resistance as a function 003aab271 typ max Fig 12. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL 5 R DSon (mΩ gate-source voltage; typical values 3 V ...

Page 8

... Fig 14. Gate charge waveform definitions 003aac647 ( (nC) G Fig 16. Input, output and reverse transfer capacitances All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL GS(pl) V GS(th GS1 GS2 ...

Page 9

... Product data sheet N-channel mΩ logic level MOSFET in LFPAK 100 150 ° 0.0 0.2 0.4 0.6 All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL 003aac640 25 °C 0.8 1.0 V (V) SD © NXP B.V. 2011. All rights reserved ...

Page 10

... A 0 2.5 scale max 4.41 2.2 0.9 0.25 0.30 4.10 4.20 3.62 2.0 0.7 0.19 0.24 3.80 REFERENCES JEDEC JEITA MO-235 All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL detail (1) (1) ( 5.0 3.3 6.2 0.85 1.3 1.27 4.8 3.1 5.8 0.40 0.8 EUROPEAN PROJECTION ...

Page 11

... N-channel mΩ logic level MOSFET in LFPAK Data sheet status Change notice Product data sheet - Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Supersedes PSMN4R0-30YL v.3 PSMN4R0-30YL v.2 © NXP B.V. 2011. All rights reserved ...

Page 12

... In case an individual agreement is concluded only the terms and conditions of the respective All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL © NXP B.V. 2011. All rights reserved ...

Page 13

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 04 — 10 March 2011 PSMN4R0-30YL Trademarks © NXP B.V. 2011. All rights reserved ...

Page 14

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 10 March 2011 Document identifier: PSMN4R0-30YL ...

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