PSMN4R0-25YLC,115 NXP Semiconductors, PSMN4R0-25YLC,115 Datasheet

MOSFET Power N-CH 25 V 4.5 mOhms LOGIC LEVEL MOSFET

PSMN4R0-25YLC,115

Manufacturer Part Number
PSMN4R0-25YLC,115
Description
MOSFET Power N-CH 25 V 4.5 mOhms LOGIC LEVEL MOSFET
Manufacturer
NXP Semiconductors
Series
-r
Datasheet

Specifications of PSMN4R0-25YLC,115

Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
4.5 mOhms
Drain-source Breakdown Voltage
25 V
Gate-source Breakdown Voltage
20 V
Continuous Drain Current
84 A
Power Dissipation
61 W
Maximum Operating Temperature
+ 175 C
Mounting Style
SMD/SMT
Package / Case
LFPAK
Gate Charge Qg
22.8 nC
Minimum Operating Temperature
- 55 C
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
4.5 mOhm @ 20A, 10V
Drain To Source Voltage (vdss)
25V
Current - Continuous Drain (id) @ 25° C
84A
Vgs(th) (max) @ Id
1.95V @ 1mA
Gate Charge (qg) @ Vgs
22.8nC @ 10V
Input Capacitance (ciss) @ Vds
1407pF @ 12V
Power - Max
61W
Mounting Type
Surface Mount
Lead Free Status / Rohs Status
 Details
Other names
934065075115

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PSMN4R0-25YLC,115
Manufacturer:
NXP
Quantity:
20 000
1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
Table 1.
Symbol
V
P
T
Static characteristics
R
I
D
j
DS
tot
DSon
PSMN4R0-25YLC
N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK
Rev. 01 — 2 December 2010
High reliability Power SO8 package,
qualified to 175°C
Low parasitic inductance and
resistance
DC-to-DC converters
Load switching
Power OR-ing
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
junction
temperature
drain-source
on-state
resistance
Conditions
T
V
see
T
V
T
V
T
j
mb
j
j
GS
GS
GS
≥ 25 °C; T
= 25 °C; see
= 25 °C; see
Figure 1
= 25 °C; see
= 10 V; T
= 4.5 V; I
= 10 V; I
j
D
≤ 175 °C
mb
D
= 20 A;
= 20 A;
Figure 12
Figure 12
= 25 °C;
Figure 2
Optimised for 4.5V Gate drive utilising
Superjunction technology
Ultra low QG, QGD & QOSS for high
system efficiencies at low and high
loads
Server power supplies
Sync rectifier
Min
-
-
-
-55
-
-
Product data sheet
Typ
-
-
-
-
4.5
3.5
Max Unit
25
84
61
175
5.8
4.5
V
A
W
°C
mΩ
mΩ

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PSMN4R0-25YLC,115 Summary of contents

Page 1

... PSMN4R0-25YLC N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK Rev. 01 — 2 December 2010 1. Product profile 1.1 General description Logic level enhancement mode N-channel MOSFET in LFPAK package. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. ...

Page 2

... Figure 15 total gate charge see DS see Figure 15 Simplified outline SOT669 (LFPAK) Description plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Min Typ = 3.5 D Figure 14 10 Figure 14; Graphic symbol D G ...

Page 3

... Figure 3 003a a f 505 120 P der (%) 150 200 Fig 2. Normalized total power dissipation as a function of mounting base temperature All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Min - = 20 kΩ - -20 Figure 1 - Figure ° -55 -55 - 200 - = 25 ° ...

Page 4

... Product data sheet N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK ( ( All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC 003a a f 519 ( =10  100  100 (V) DS © NXP B.V. 2010. All rights reserved. 003a a f 506 ...

Page 5

... Transient thermal impedance from junction to mounting base as a function of pulse duration PSMN4R0-25YLC Product data sheet N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK Conditions see Figure All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Min Typ Max - 1.4 2.4 003a a f 507 t p  ...

Page 6

... Figure 14; see Figure 4 see Figure 14; see Figure see Figure 14; DS see Figure MHz °C; see Figure 16 j All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Min Typ Max 22 1.05 1.53 1. 100 - - 100 - - 100 - 4.5 5 ...

Page 7

... (m ( 2.6 2 (V) DS Fig 7. Drain-source on-state resistance as a function of gate-source voltage; typical values All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Min Typ - 15 9.9 - 7. 24.5 - 16.1 - 14.9 - 9.6 003a a f 509 ...

Page 8

... N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK 003a a f 514 (A) D Fig 9. 003a a f 513 V Max (V) GS Fig 11. Gate-source threshold voltage as a function of All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC ( 150 Transfer characteristics; drain current as a function of gate-source voltage; typical values 4 ...

Page 9

... V (V) = 3 (A) D Fig 13. Normalized drain-source on-state resistance 003aaa508 Fig 15. Gate-source voltage as a function of gate All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC =4.5V GS 1.5 1 0 factor as a function of junction temperature 10 GS (V) 8 12V ...

Page 10

... N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK 003a a f 515 I ( (V) DS Fig 17. Source current as a function of source-drain All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC 150 0.3 0.6 0.9 voltage; typical values 003a a f 444 003a a f 518 = ...

Page 11

... D max 4.41 2.2 0.9 0.25 0.30 4.10 4.20 3.62 2.0 0.7 0.19 0.24 3.80 REFERENCES JEDEC JEITA MO-235 All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC detail (1) (1) ( 5.0 3.3 6.2 0.85 1.3 1.27 4.8 3.1 5 ...

Page 12

... NXP Semiconductors 8. Revision history Table 7. Revision history Document ID Release date PSMN4R0-25YLC v.1 20101202 PSMN4R0-25YLC Product data sheet N-channel 25 V 4.5 mΩ logic level MOSFET in LFPAK Data sheet status Change notice Product data sheet - All information provided in this document is subject to legal disclaimers. ...

Page 13

... In case an individual agreement is concluded only the terms and conditions of the respective All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC © NXP B.V. 2010. All rights reserved ...

Page 14

... TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V. HD Radio and HD Radio logo — are trademarks of iBiquity Digital Corporation. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 2 December 2010 PSMN4R0-25YLC Trademarks © NXP B.V. 2010. All rights reserved ...

Page 15

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 2 December 2010 Document identifier: PSMN4R0-25YLC ...

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