P89LPC932A1 NXP Semiconductors, P89LPC932A1 Datasheet - Page 9

• Manufacturer Part Number: P89LPC932A1
• Description: The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, basedon a high performance processor architecture that executes instructions in two to fourclocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 2.
P89LPC932A1_3
Product data sheet
Symbol
P1.5/RST
P1.6/OCB
P1.7/OCC
P2.0 to P2.7
P2.0/ICB
P2.1/OCD
P2.2/MOSI
P2.3/MISO
P2.4/SS
P2.5/SPICLK
P2.6/OCA
Pin description
Pin
TSSOP28,
PLCC28,
DIP28
6
5
4
1
2
13
14
15
16
27
…continued
HVQFN28
2
1
28
25
26
9
10
11
12
23
Type Description
I
I
I/O
O
I/O
O
I/O
I/O
I
I/O
O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
O
P1.5 — Port 1 bit 5 (input only).
RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their default
states, and the processor begins execution at address 0. Also used during
a power-on sequence to force ISP mode. When using an oscillator
frequency above 12 MHz, the reset input function of P1.5 must be
enabled. An external circuit is required to hold the device in reset at
power-up until V
power is removed V
operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit
may be required to hold the device in reset when V
minimum specified operating voltage.
P1.6 — Port 1 bit 6.
OCB — Output Compare B.
P1.7 — Port 1 bit 7.
OCC — Output Compare C.
Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to
and
All pins have Schmitt trigger inputs.
Port 2 also provides various special functions as described below:
P2.0 — Port 2 bit 0.
ICB — Input Capture B.
P2.1 — Port 2 bit 1.
OCD — Output Compare D.
P2.2 — Port 2 bit 2.
MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.3 — Port 2 bit 3.
MISO — When configured as master, this pin is input, when configured as
slave, this pin is output.
P2.4 — Port 2 bit 4.
SS — SPI Slave select.
P2.5 — Port 2 bit 5.
SPICLK — SPI clock. When configured as master, this pin is output; when
configured as slave, this pin is input.
P2.6 — Port 2 bit 6.
OCA — Output Compare A.
Rev. 03 — 12 March 2007
8-bit microcontroller with accelerated two-clock 80C51 core
Table 8 “Static characteristics”
DD
has reached its specified level. When system
DD
will fall below the minimum specified
Section 7.13.1 “Port configurations”
for details.
P89LPC932A1
© NXP B.V. 2007. All rights reserved.
DD
falls below the
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