P89LPC932A1 NXP Semiconductors, P89LPC932A1 Datasheet - Page 29
![no-image](/images/manufacturer_photos/0/4/487/nxp_semiconductors_sml.jpg)
P89LPC932A1
Manufacturer Part Number
P89LPC932A1
Description
The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, basedon a high performance processor architecture that executes instructions in two to fourclocks, six times the rate of standard 80C51 devices
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC932A1.pdf
(64 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P89LPC932A1
Manufacturer:
PHAEDRUS
Quantity:
185
Part Number:
P89LPC932A1FA
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
P89LPC932A1FA,112
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P89LPC932A1FA,129
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Company:
Part Number:
P89LPC932A1FAЈ¬112
Manufacturer:
NXP
Quantity:
9 947
Company:
Part Number:
P89LPC932A1FDH
Manufacturer:
VISHAY
Quantity:
120 000
Part Number:
P89LPC932A1FDH
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Company:
Part Number:
P89LPC932A1FDHЈ¬512
Manufacturer:
NXP
Quantity:
836
Company:
Part Number:
P89LPC932A1FHN
Manufacturer:
IR
Quantity:
4 510
NXP Semiconductors
P89LPC932A1_3
Product data sheet
7.19.7 Alternating output mode
7.19.8 PLL operation
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in
Where: N is the value of PLLDV[3:0].
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to
PLL frequency
Fig 11. Alternate output mode
=
----------------- -
PCLK
N
+
1
Rev. 03 — 12 March 2007
8-bit microcontroller with accelerated two-clock 80C51 core
002aaa895
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
0
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
P89LPC932A1
TIMER VALUE
© NXP B.V. 2007. All rights reserved.
Equation
1.
PCLK
29 of 64
(1)
16
.