LPC2921_23_25 NXP Semiconductors, LPC2921_23_25 Datasheet - Page 41

• Manufacturer Part Number: LPC2921_23_25
• Description: The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
Fig 8.
AHB2DTL
BRIDGE
Power, Clock, and Reset control SubSystem (PCRSS) block diagram
6.15.1 Clock description
reset from watchdog counter
OSCILLATOR
LOW POWER
OSCILLATOR
REGISTERS
REGISTERS
EXTERNAL
RST (device pin)
The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the
AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and
PMU internal logic, see
BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is
derived from BASE_PCR_CLK and is always on in order to be able to wake up from
low-power modes.
RING
CGU0
RGU
POR
FDIV[6:0]
PLL
All information provided in this document is subject to legal disclaimers.
RESET OUTPUT
DELAY LOGIC
DEGLITCH/
INPUT
SYNC
Rev. 03 — 14 April 2010
Section
OUT11
OUT6
OUT0
OUT1
OUT5
OUT7
OUT9
CGU0
RGU
6.7.2. CLK_SYS_PCRSS is derived from
ARM9 microcontroller with CAN, LIN, and USB
FDIV
PLL
OUT0
OUT2
LPC2921/2923/2925
CGU1
WARM_RST
PCR_RST
COLD_RST
RGU_RST
POR_RST
AHB_RST
SCU_RST
REGISTERS
CONTROL
ENABLE
CLOCK
CLOCK
GATES
PMU
© NXP B.V. 2010. All rights reserved.
PMU
002aae249
wakeup_a
disable:
grant
request
master
branch
clocks
AHB
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