LPC2921_23_25 NXP Semiconductors, LPC2921_23_25 Datasheet - Page 21

• Manufacturer Part Number: LPC2921_23_25
• Description: The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.10.2 Pin description
6.10.3 Clock description
The USB device controller has the following features:
Table 11.
Access to the USB registers is clocked by the CLK_SYS_USB, derived from
BASE_SYS_CLK, see
the USB block, BASE_USB_CLK (see
Pin name
USB_VBUS
USB_D+
USB_D−
USB_CONNECT
USB_UP_LED
•
•
•
•
•
•
•
•
•
•
Fully compliant with USB 2.0 specification (full speed).
Supports 32 physical (16 logical) endpoints with a 2 kB endpoint buffer RAM.
Supports Control, Bulk, Interrupt and Isochronous endpoints.
Scalable realization of endpoints at run time.
Endpoint Maximum packet size selection (up to USB maximum specification) by
software at run time.
Supports SoftConnect and GoodLink features.
While USB is in the Suspend mode, the LPC2921/2923/2925 can enter the reduced
power mode and wake up on USB activity.
Supports DMA transfers with the on-chip SRAM blocks on all non-control endpoints.
Allows dynamic switching between CPU-controlled slave and DMA modes.
Double buffer implementation for Bulk and Isochronous endpoints.
USB device port pins
All information provided in this document is subject to legal disclaimers.
Direction
I
I/O
I/O
O
O
Section
Rev. 03 — 14 April 2010
6.7.2. The CGU1 provides an independent base clock to
Description
USB_VBUS status input. When this function is not enabled
via its corresponding PINSEL register, it is driven HIGH
internally.
positive differential data
negative differential data
SoftConnect control signal
GoodLink LED control signal
Section
ARM9 microcontroller with CAN, LIN, and USB
6.15.3).
LPC2921/2923/2925
© NXP B.V. 2010. All rights reserved.
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