LPC2921_23_25 NXP Semiconductors, LPC2921_23_25 Datasheet
LPC2921_23_25
Related parts for LPC2921_23_25
LPC2921_23_25 Summary of contents
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LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB Rev. 03 — 14 April 2010 1. General description The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...
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... CPU operating voltage: 1.8 V ± I/O operating voltage: 2 3.6 V; inputs tolerant up to 5.5 V. 100-pin LQFP package. −40 °C to +85 °C ambient operating temperature range. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 © ...
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... LPC2925FBD100 LQFP100 3.1 Ordering options Table 2. Type number LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Part options Flash SRAM (incl. memory ETB SRAM) 128 kB ...
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... V ADC1/2 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. LPC2921/2923/2925 block diagram LPC2921_23_25_3 Product data sheet JTAG interface TEST/DEBUG INTERFACE ITCM DTCM 8 kB SRAM ARM968E-S 1 master 2 slaves master ...
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... P0[29]/CAP0[1]/ 7 MAT0[ DD(IO) [1] P0[30]/CAP0[2]/ 9 MAT0[2] [1] P0[31]/CAP0[3]/ 10 MAT0[ SS(IO) LPC2921_23_25_3 Product data sheet 1 LPC2921FBD100 LPC2923FBD100 LPC2925FBD100 25 Pin configuration for SOT407-1 (LQFP100) Description Function 0 (default) Function 1 IEEE 1149.1 test data out GPIO0, pin 24 UART1 TXD GPIO0, pin 25 UART1 RXD GPIO0, pin 26 - GPIO0, pin 27 ...
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... P1[14]/CAP2[0]/ 35 SCS0[3] [1] P1[13]/EI3/SCL1 36 [1] P1[12]/EI2/SDA1 DD(IO) [1] P1[11]/SCK1/SCL0 39 LPC2921_23_25_3 Product data sheet …continued Description Function 0 (default) Function 1 GPIO5, pin 19 USB_D+ GPIO5, pin 18 USB_D− 3.3 V power supply for I/O 1.8 V power supply for digital core ground for core ground for I/O GPIO1, pin 27 TIMER1 CAP2, ...
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... P0[4]/PMAT0[2] 69 [1] P0[5]/PMAT0[ DD(IO) [1] P0[6]/PMAT0[4] 72 [1] P0[7]/PMAT0[5] 73 LPC2921_23_25_3 Product data sheet …continued Description Function 0 (default) Function 1 GPIO1, pin 10 SPI1 SDI ground for digital core 1.8 V power supply for digital core GPIO1, pin 9 SPI1 SDO ground for I/O GPIO1, pin 8 SPI1 SCS0 GPIO1, pin 7 ...
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... PMAT2[3] [4] P0[22]/IN2[6]/ 97 PMAT2[4]/A18 V 98 SS(IO) LPC2921_23_25_3 Product data sheet …continued Description Function 0 (default) Function 1 3.3 V power supply for ADC TAP controller select input; LOW-level selects the ARM debug mode; HIGH-level selects boundary scan; pulled up internally. not connected to a function; must be tied to 3.3 V power supply for ADC V ...
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... Amongst the most compelling features of the ARM968E-S are: • Separate directly connected instruction and data Tightly Coupled Memory (TCM) interfaces. LPC2921_23_25_3 Product data sheet …continued Description Function 0 (default) Function 1 GPIO0, pin 23 ADC2 IN7 IEEE 1149 ...
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... They may be used for code and/or data storage. The 8 kB SRAM block for the ETB can be used as static memory for code and data storage as well. However, DMA access to this memory region is not supported. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — ...
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Memory map LPC2921/2923/2925 0xFFFF FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature encoder 0xE00C 9000 PWM3 0xE00C 8000 PWM2 0xE00C ...
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... JTAGSEL TRST TMS TDI TDO TCK 1. Only for 1.8 V power sources LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 8 for trip levels of the internal power-up reset circuit for characteristics of the several start-up and initialization times. Reset pin Direction ...
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... Management Unit (PMU) and can be controlled independently. Branch clocks derived from the same base clock are synchronous in frequency and phase. See more details of clock and power control within the device. LPC2921_23_25_3 Product data sheet shows the power supply pins. Power supply pins Description digital core supply 1 ...
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... LPC2921/2923/2925 overview of clock areas 6.7.2 Base clock and branch clock relationship Table 7 derived branch clocks. A short description is given of the hardware parts that are clocked with the individual branch clocks. In relevant cases more detailed information can be LPC2921_23_25_3 Product data sheet BASE_ICLK0_CLK BASE_SYS_CLK BASE_ICLK1_CLK ...
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... See Section 6.15.5 Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB for more details of how to control the individual branch clocks. Base clock and branch clock overview Branch clock name CLK_SAFE CLK_SYS_CPU ...
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... In the Power, Clock and Reset control SubSystem (PCRSS) parts of the CGU, RGU, and PMU have their own clock source. See Table 8. Base clock BASE_OUT_CLK BASE_USB_CLK LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Base clock and branch clock overview Branch clock name CLK_MSCSS_APB ...
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... When an AHB data port read transfer requires data from a different flash word to that involved in the previous read transfer, a new flash read is done and wait states are given until the new read data is available. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. Rev. 03 — ...
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... Flash memory sector number LPC2921_23_25_3 Product data sheet Table Flash read modes for single (non-linear) reads; one flash-word read per word read default mode of operation; most recently read flash word is kept until another flash word is required one flash-word read per word read ...
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... Pin description The flash memory controller has no external pins. However, the flash can be programmed via the JTAG pins, see 6.8.5 Clock description The flash memory controller is clocked by CLK_SYS_FMC, see LPC2921_23_25_3 Product data sheet Flash sector overview …continued Sector size (kB) Flash memory ...
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... The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. LPC2921_23_25_3 Product data sheet 6.7.2. All information provided in this document is subject to legal disclaimers. ...
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... USB_D− USB_CONNECT USB_UP_LED 6.10.3 Clock description Access to the USB registers is clocked by the CLK_SYS_USB, derived from BASE_SYS_CLK, see the USB block, BASE_USB_CLK (see LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB USB device port pins Direction Description I USB_VBUS status input. When this function is not enabled via its corresponding PINSEL register driven HIGH internally ...
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... The event router allows the event source to be defined, its polarity and activation type to be selected and the interrupt to be masked or enabled. The event router can be used to start a clock on an external event. The vectored interrupt-controller inputs are active HIGH. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 2 C-bus SCL pins plus three internal event sources ...
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... Internal chip reset if not periodically triggered • Timer counter register runs on always-on safe clock • Optional interrupt generation on watchdog time-out • Debug mode with disabling of reset LPC2921_23_25_3 Product data sheet shows the pins connected to the event router. Event-router pin connections Direction Description I ...
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... Reset timer on match with optional interrupt generation. • four external outputs per timer corresponding to match registers, with the following capabilities: – Set LOW on match. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.15.4. 6.7.2. The register interface towards the system bus is clocked by Section All information provided in this document is subject to legal disclaimers ...
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... CLK_SYS_PESS. The timer and prescale counters are clocked by CLK_TMRx. 6.12.4 UARTs The LPC2921/2923/2925 contains two identical UARTs located at different peripheral base addresses. The key features are: • 16-byte receive and transmit FIFOs. LPC2921_23_25_3 Product data sheet Section 6.15.5 shows the timer pins (x runs from 0 to 3). Timer pins Pin name Direction ...
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... Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts. Serial clock-rate master mode: fserial_clk ≤ f • • Serial clock-rate slave mode: fserial_clk = f LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.13.2). Table 14 shows the UART pins (x runs from 0 to 1). ...
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... Direction of SPIx SCS and SPIx SCK pins depends on master or slave mode. These pins are output in master mode, input in slave mode. [2] In slave mode there is only one chip select input pin, SPIx SCS0. The other chip selects have no function in slave mode. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.11.3. ...
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... LPC2921/2923/2925. shows the GPIO pins. Table 16. Symbol GPIO0 pin[31:0] GPIO1 pin[27:0] GPIO5 pin[19:18] LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6.7.2. Note that each SPI has its own CLK_SPIx branch clock for GPIO pins Pin name ...
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... LPC2921/2923/2925. Table 17 Table 17. Symbol CANx TXD CANx RXD LPC2921_23_25_3 Product data sheet 6.7.2. Note that each GPIO has its own CLK__SYS_GPIOx branch clock for shows the CAN pins (x runs from 0 to 1). CAN pins Pin name ...
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... C0 and I and do not support powering off of individual devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Table 18 shows the LIN pins. For more information see LIN controller pins ...
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... PWMs. These carrier patterns can be used, for example, in applications requiring current control. Several other trigger possibilities are provided for the ADCs (external, cascaded or following a PWM). The capture inputs of both timers can also be used to capture the start pulse of the ADCs. LPC2921_23_25_3 Product data sheet 2 C-bus can be used for test and diagnostic purposes. ...
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... To support applications like motor control, a mechanism to synchronize several PWMs and ADCs is available (sync_in and sync_out). Note that the PWMs run on the PWM clock and the ADCs on the ADC clock, see Section LPC2921_23_25_3 Product data sheet 6.15.2. All information provided in this document is subject to legal disclaimers. ...
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... PAUSE Fig 5. Modulation and Sampling Control SubSystem (MSCSS) block diagram 6.14.2 Pin description The pins of the LPC2921/2923/2925 MSCSS associated with the two ADC modules are described in Section Section Section LPC2921_23_25_3 Product data sheet AHB-TO-APB BRIDGE MSCSS QEI start ADC1 MSCSS TIMER0 ...
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... ADC clock. This split into two clock domains affects the behavior from a system-level perspective. The actual analog-to-digital conversions take place in the ADC clock domain, but system control takes place in the system clock domain. LPC2921_23_25_3 Product data sheet 6.7.2. ...
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... VREFN VREFP V DDA(ADC3V3) Remark: Note that the ADC1 and ADC2 accept an input voltage 3.6 V (see Table 31) on the ADC1/2 IN pins. If the ADC is not used, the pins are 5 V tolerant. LPC2921_23_25_3 Product data sheet Section 6.15.2. Section 6.14 ADC clock (up to 4.5 MHz) (BASE_ADC_CLK) ...
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... Dimmer controller: The flexibility of providing waves of a desired duty cycle and cycle period allows the PWM to control the amount of power to be transferred to the load. The PWM functions as a dimmer controller in this application. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section 6 ...
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... Several PWMs can be synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports. See Figure 5 LPC2921/2923/2925. PWM0 can be master over PWM1; PWM1 can be master over PWM2, etc. LPC2921_23_25_3 Product data sheet APB DOMAIN update capture data PWM ...
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... These signals are instead connected to the ADC and PWM modules as outlined in the description of the MSCSS, see See Section 6.12.3 LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB PWM pins Pin name ...
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... Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). • Connected to APB. LPC2921_23_25_3 Product data sheet MSCSS timer 1 pin Direction Description IN pause pin for MSCSS timer 1 6.7.2. Note that each timer has its own CLK_MSCSS_MTMRx branch clock for All information provided in this document is subject to legal disclaimers. Rev. 03 — ...
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... The Power, Clock, and Reset control SubSystem (PCRSS) in the LPC2921/2923/2925 includes a Clock Generator Unit (CGU), a Reset Generator Unit (RGU) and a Power Management Unit (PMU). Figure 8 communication with the AHB system bus. LPC2921_23_25_3 Product data sheet QEI pins Pin name Direction PHA0 ...
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... AHB side of the AHB to DTL bus bridge and CLK_PCR_SLOW clocks the CGU, RGU and PMU internal logic, see BASE_SYS_CLK, which can be switched off in low-power modes. CLK_PCR_SLOW is derived from BASE_PCR_CLK and is always on in order to be able to wake up from low-power modes. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB CGU0 PLL ...
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... Maximum frequency that guarantees stable operation of the LPC2921/2923/2925. [2] Fixed to low-power oscillator. For generation of these base clocks, the CGU consists of primary and secondary clock generators and one output generator for each base clock. LPC2921_23_25_3 Product data sheet CGU0 base clocks Frequency (MHz) BASE_SAFE_CLK 0 ...
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... The crystal oscillator can be used as source for high-frequency clocks external clock input if a crystal is not connected. Secondary clock generators are a PLL and seven fractional dividers (FDIV[0:6]). The PLL has three clock outputs: normal, 120° phase-shifted and 240° phase-shifted. LPC2921_23_25_3 Product data sheet FDIV0 clkout ...
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... Clock Activity Detection: and values of ‘CLK_SEL’ that would select those clocks are masked and not written to the control registers. This is accomplished by adding a clock detector to every clock LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB For every output generator generating the base clocks a ...
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... PLL has locked onto the input clock. 2. Generation of the main clock is restricted by the frequency range of the PLL clock input. See LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Provisions are included in the CGU to allow clocks to be Figure . These clocks are either divided by 2 × ...
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... LOCK signal high once it has regained lock on the input clock. 6.15.2.3 Pin description The CGU0 module in the LPC2921/2923/2925 has the pins listed in Table 25. Symbol XOUT_OSC XIN_OSC LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB PSEL bits / 2PDIV bypass / MDIV MSEL bits ...
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... The key features of the Reset Generation Unit (RGU) are: • Reset controlled individually per subsystem • Automatic reset stretching and release • Monitor function to trace resets back to source LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB (CGU1) clkout clkout120 FDIV0 ...
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... DMA_RST USB_RST VIC_RST AHB_RST 6.15.4.2 Pin description The RGU module in the LPC2921/2923/2925 has the following pins. RGU pins. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Reset output configuration Reset source power-on reset module POR_RST, RST_N pin RGU_RST, WATCHDOG PCR internal; source for COLD_RST ...
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... Remark: For any disabled branch clocks to be re-activated their corresponding base clocks must be running (controlled by the CGU0). Table 29 Every branch clock is related to one particular base clock not possible to switch the source of a branch clock in the PMU. LPC2921_23_25_3 Product data sheet RGU pins Direction Description IN external reset input, active LOW ...
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... CLK_IVNSS_I2C1 CLK_IVNSS_LIN0 CLK_IVNSS_LIN1 CLK_MSCSS_APB CLK_MSCSS_MTMR0 CLK_MSCSS_MTMR1 CLK_MSCSS_PWM0 CLK_MSCSS_PWM1 CLK_MSCSS_PWM2 CLK_MSCSS_PWM3 CLK_MSCSS_ADC1_APB BASE_MSCSS_CLK CLK_MSCSS_ADC2_APB BASE_MSCSS_CLK CLK_MSCSS_QEI CLK_OUT_CLK LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Branch clock overview Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK BASE_SYS_CLK ...
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... The interrupt target is configured for each interrupt request input of the VIC. The targets are defined as follows: • Target 0 is ARM processor FIQ (fast interrupt service). • Target 1 is ARM processor IRQ (standard interrupt service). LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Branch clock overview …continued Base clock ...
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... Software emulation of an interrupt-requesting device, including interrupts. 6.16.2 Clock description The VIC is clocked by CLK_SYS_VIC, see LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Section All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 6 ...
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... LOW-level short-circuit OLS output current General T storage temperature stg T ambient temperature amb LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Conditions average value per supply pin average value per ground pin for ADC1/2: I/O port 0 pin 8 to pin 23. ...
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... should not be exceeded. DD(IO) SS(IO) [7] Human-body model: discharging a 100 pF capacitor via a 10 kΩ series resistor. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Conditions on all pins human body model charged device model on corner pins charged device model ...
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... Input pins and I/O pins configured as input V input voltage I V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys LPC2921_23_25_3 Product data sheet = DDA(ADC3V3) Conditions Device state after reset; system clock °C; 125 MHz; T amb executing code while(1){} from flash. ...
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... OH V LOW-level output voltage (driven) for OL I HIGH-level output current LOW-level output current OL I HIGH-level short-circuit OHS output current LPC2921_23_25_3 Product data sheet …continued = DDA(ADC3V3) Conditions all port pins 3 5.5 V; see Figure 20 I all port pins, RST, TRST, ...
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... This parameter is not part of production testing or final testing, hence only a typical value is stated. Maximum and minimum values are based on simulation results. [8] The power-up reset has a time filter: V for 11 μs before internal reset is asserted. V trip(low) LPC2921_23_25_3 Product data sheet …continued = DDA(ADC3V3) Conditions drive high ...
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... T ADC and the ideal transfer curve. See [8] See Figure 13. ADC IN[y] Fig 13. Suggested ADC interface - LPC2921/2923/2925 ADC1/2 IN[y] pin LPC2921_23_25_3 Product data sheet − ° ° +85 C unless otherwise specified; ADC frequency 4.5 MHz. ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 14. ADC characteristics LPC2921_23_25_3 Product data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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... NXP Semiconductors 8.1 Power consumption I DD(CORE) (mA) Fig 15 DD(CORE) (mA) Fig 16. I LPC2921_23_25_3 Product data sheet °C; active mode entered executing code from flash; core voltage 1.8 V; all Conditions: T amb peripherals enabled but not configured to run. at different core frequencies (active mode) ...
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... NXP Semiconductors I DD(CORE) (mA) Fig 17. 8.2 Electrical pin characteristics V (mV) Fig 18. Typical LOW-level output voltage versus LOW-level output current LPC2921_23_25_3 Product data sheet 80 125 MHz 60 100 MHz 80 MHz 40 40 MHz 20 10 MHz 0 −40 −15 10 Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run ...
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... NXP Semiconductors V Fig 19. Typical HIGH-level output voltage versus HIGH-level output current I (μA) Fig 20. Typical pull-down current versus temperature LPC2921_23_25_3 Product data sheet 3.5 OH (V) 3.0 2.5 2.0 1.0 2 3.3 V. DD(IO) 80 I(pd −40 − 3 All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 ...
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... NXP Semiconductors I (μA) Fig 21. Typical pull-up current versus temperature LPC2921_23_25_3 Product data sheet −20 I(pu) −40 −60 −80 −100 −40 − All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB ...
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... This parameter is not part of production testing or final testing, hence only a typical value is stated. [4] Oscillator start-up time depends on the quality of the crystal. For most crystals it takes about 1000 clock pulses until the clock is fully stable. LPC2921_23_25_3 Product data sheet = 3.6 V; all voltages are measured with respect to ...
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... NXP Semiconductors f ref(RO) (kHz) Fig 22. Low-power ring oscillator thermal characteristics LPC2921_23_25_3 Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB 1 ...
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... EOPR1 t EOP width at receiver EOPR2 [1] Characterized but not implemented as production test. Guaranteed by design. T PERIOD differential data lines Fig 23. Differential data-to-EOP transition skew and EOP width LPC2921_23_25_3 Product data sheet , unless otherwise specified. DD(3V3) Conditions see ...
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... Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] [3] Bus capacitance C in pF, from 400 pF. b LPC2921_23_25_3 Product data sheet 2 C-bus interface 2 C-bus pins = 3.6 V ...
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... Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. shifting edges SCKn SDOn SDIn Fig 24. SPI data input set-up time in SSP Master mode LPC2921_23_25_3 Product data sheet = DDA(ADC3V3) Conditions master operation slave operation = 25 ° ...
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... Number of program/erase cycles. Table 38. − amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2921_23_25_3 Product data sheet Flash characteristics ° ° + DD(CORE) DD(OSC_PLL 3.6 V; all voltages are measured with respect to ground. Parameter Conditions endurance retention time powered unpowered programming time ...
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... V. Figure 26 LPC2921/2923/2925 by controlling the temperature and the core voltage accordingly. core frequency (MHz) Fig 25. Core operating frequency versus temperature for different core voltages LPC2921_23_25_3 Product data sheet = 3.6 V; all voltages are measured with respect to DDA(ADC3V3) Conditions f = 4.5 MHz ...
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... NXP Semiconductors core frequency (MHz) Fig 26. Core operating frequency versus core voltage for different temperatures 10.2 Suggested USB interface solutions LPC29xx Fig 27. LPC2921/2923/2925 USB interface on a self-powered device LPC2921_23_25_3 Product data sheet 145 135 25 °C 45 °C 65 °C 85 °C 125 115 105 1.65 1.75 V DD(IO) USB_UP_LED ...
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... NXP Semiconductors LPC29xx Fig 28. LPC2921/2923/2925 USB interface on a bus-powered device 10.3 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 29. SPI timing in master mode LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO USB_UP_LED 1.5 kΩ USB_VBUS Ω ...
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... NXP Semiconductors SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 30. SPI timing in slave mode LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SDIn MSB IN SDOn MSB OUT SDIn MSB IN DATA VALID SDOn MSB OUT DATA VALID All information provided in this document is subject to legal disclaimers. ...
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... PCB as small as possible. Also parasitics should stay as small as possible. Values of C smaller accordingly to the increase in parasitics of the PCB layout. LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB which attenuates the input voltage by a factor C ...
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... A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT407-1 136E20 Fig 32. Package outline (LQFP100) LPC2921_23_25_3 Product data sheet ...
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... Solder bath specifications, including temperature and impurities LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB All information provided in this document is subject to legal disclaimers. ...
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... Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB and 41 SnPb eutectic process (from J-STD-020C) Package reflow temperature (° ...
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... NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2921_23_25_3 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... CAN — ISO 11898-1: 2002 road vehicles - Controller Area Network (CAN) - part 1: data link layer and physical signalling [5] LIN — LIN specification package, revision 2.0 LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB Abbreviations list Description Acceptance Filter ...
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... USB logo added. 20091208 Product data sheet 20090615 Preliminary data sheet - All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB Change notice Supersedes LPC2921_23_25_2 - LPC2921_23_25_1 - © NXP B.V. 2010. All rights reserved ...
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... Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB [3] Definition This document contains data from the objective specification for product development ...
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... NXP Semiconductors’ product specifications. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners ...
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... General subsystem 6.11.1 General subsystem clock description . . . . . . . 22 6.11.2 Chip and feature identification . . . . . . . . . . . . 22 6.11.3 System Control Unit (SCU 6.11.4 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.11.4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 23 6.12 Peripheral subsystem . . . . . . . . . . . . . . . . . . . 23 LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB 6.12.1 Peripheral subsystem clock description 6.12.2 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 23 6.12.2.1 Functional description . . . . . . . . . . . . . . . . . . 24 6.12.2.2 Clock description . . . . . . . . . . . . . . . . . . . . . . 24 6.12.3 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 ...
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... NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC2921/2923/2925 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 81 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Contact information . . . . . . . . . . . . . . . . . . . . 82 Contents Date of release: 14 April 2010 Document identifier: LPC2921_23_25_3 All rights reserved. ...