ADP1048 Analog Devices, ADP1048 Datasheet - Page 77

• Manufacturer Part Number: ADP1048
• Description: Digital Power Factor Correction Controller with accurate AC Power Metering
• Manufacturer: Analog Devices

Data Sheet
SMART_VOUT_SUPER_HIGH_LINE_HYS REGISTER
Table 138. Register 0xFE4D—SMART_VOUT_SUPER_HIGH_LINE_HYS
Bits
[7:0]
POWER_HYS REGISTER
Table 139. Register 0xFE4E—POWER_HYS
Bits
[7:0]
ADVANCED FEATURE ENABLE REGISTER
Table 140. Register 0xFE4F—Advanced Feature Enable
Bits
7
6
5
4
3
2
1
0
VOUT_OV_FAULT_HYS REGISTER
Table 141. Register 0xFE50—VOUT_OV_FAULT_HYS
Bits
[7:0]
VIN_UV_FAULT_HYS REGISTER
Table 142. Register 0xFE51—VIN_UV_FAULT_HYS
Bits
[7:0]
Bit Name
VOUT OV fault hysteresis
Bit Name
VIN UV fault hysteresis
Bit Name
Super high line
voltage hysteresis
Bit Name
Power hysteresis
Bit Name
RSVD
Enable current loop
feedforward
Enable light load
current loop filter
Enable phase
shedding
Enable smart
switching frequency
Enable smart output
voltage
Enable PWM
synchronization
Enable frequency
dithering
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
These bits set the voltage hysteresis of the super high line voltage for the smart output voltage
function. The output voltage is VOH2 if the input voltage is lower than the super high line
voltage minus the voltage hysteresis.
Description
These bits set the power hysteresis for low power mode operation. The PFC exits the low power
mode if the input power is higher than the low power threshold plus the power hysteresis.
Description
Reserved.
1 = current loop feedforward is enabled.
0 = current loop feedforward is disabled.
1 = light load current loop filter is enabled.
0 = light load current loop filter is disabled.
1 = phase shedding is enabled.
0 = phase shedding is disabled.
This bit applies to the
1 = smart switching frequency is enabled.
0 = smart switching frequency is disabled.
1 = smart output voltage is enabled.
0 = smart output voltage is disabled.
1 = PWM frequency synchronization is enabled.
0 = PWM frequency synchronization is disabled.
1 = frequency dithering is enabled.
0 = frequency dithering is disabled.
Description
This register determines the mantissa hysteresis for the VOUT_OV_FAULT_LIMIT condition. This
hysteresis applies only when the disable output option is selected as the VOUT_OV_FAULT_
RESPONSE (Register 0x41, Bits[7:6]). The PFC output is reenabled when the output voltage is
lower than VOUT_OV_FAULT_LIMIT minus this hysteresis.
Description
This register determines the mantissa hysteresis for the VIN_UV_FAULT_LIMIT condition. This
hysteresis applies only when the disable output option is selected as the VIN_UV_FAULT_
RESPONSE (Register 0x5A, Bits[7:6]). The PFC output is reenabled when the input voltage is
higher than VIN_UV_FAULT_LIMIT plus this hysteresis.
Rev. 0 | Page 77 of 84
ADP1048
only.
ADP1047/ADP1048