ADP1048 Analog Devices, ADP1048 Datasheet - Page 36

• Manufacturer Part Number: ADP1048
• Description: Digital Power Factor Correction Controller with accurate AC Power Metering
• Manufacturer: Analog Devices

ADP1047/ADP1048
Clock Generation and Stretching
The
overall system; therefore, the device never needs to generate the
clock, which is done by the master device in the system. How-
ever, the PMBus slave device is capable of clock stretching to
put the master in a wait state. By stretching the SCL signal
during the low period, the slave device communicates to the
master device that it is not ready and that the master device
must wait.
Conditions where the PMBus slave device stretches the SCL line
low include the following:
•
•
•
Note that the slave device can stretch the SCL line only during
the low period. Also, whereas the I
indefinite stretching of the SCL line, the PMBus specification
limits the maximum time that the SCL line can be stretched,
or held low, to 25 ms, after which the device must release the
communication lines and reset its state machine.
GENERAL CALL SUPPORT
The PMBus slave is capable of decoding and acknowledging
a general call address. The PMBus device responds to both its
own address and the general call address (0x00). The general
call address enables all devices on the PMBus to be written to
simultaneously.
Note that all PMBus commands must start with the slave
address with the R/ W bit cleared (set to 0), followed by the
command code. This is also true when using the general call
address to communicate with the PMBus slave device.
ADP1047/ADP1048
The master device is transmitting at a higher baud rate
than the slave device.
The receive buffer of the slave device is full and must be
read before continuing. This prevents a data overflow
condition.
The slave device is not ready to send data that the master
has requested.
S
MASTER TO SLAVE
SLAVE TO MASTER
ADDRESS
SLAVE
are always PMBus slave devices in the
W
A
2
C specification allows
COMMAND
CODE
A
Sr
ADDRESS
SLAVE
Figure 42. Block Read Protocol
Rev. 0 | Page 36 of 84
R
A
BYTE COUNT
= N
FAST MODE
Fast mode (400 kHz) uses essentially the same mechanics as
the standard mode of operation; the electrical specifications
and timing are most affected. The PMBus slave is capable of
communicating with a master device operating in standard
mode (100 kHz) or fast mode.
FAULT CONDITIONS
The PMBus protocol provides a comprehensive set of fault
conditions that must be monitored and reported. These fault
conditions can be grouped into two major categories: commu-
nication faults and monitoring faults.
Communication faults are error conditions associated with the
data transfer mechanism of the PMBus protocol. Monitoring
faults are error conditions associated with the operation of the
PMBus device, such as output overvoltage protection, and are
specific to each PMBus device. These fault conditions are
described in the Power Supply System and Fault Monitoring
section.
TIMEOUT CONDITION
A timeout condition occurs if any single SCL clock pulse is held
low for longer than the t
the timeout condition, the PMBus slave device has 10 ms to abort
the transfer, release the bus lines, and be ready to accept a new
start condition. The device initiating the timeout is required to
hold the SCL clock line low for at least t
guaranteeing that the slave device is given enough time to reset
its communication protocol.
A
DATA BYTE 1
A
TIMEOUT
DATA BYTE N
of 25 ms (min). Upon detecting
TIMEOUT MAX
A
P
Data Sheet
= 35 ms,