ADP1048 Analog Devices, ADP1048 Datasheet - Page 76
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
ADP1048
Manufacturer Part Number
ADP1048
Description
Digital Power Factor Correction Controller with accurate AC Power Metering
Manufacturer
Analog Devices
Datasheet
1.ADP1047.pdf
(84 pages)
- Current page: 76 of 84
- Download datasheet (2Mb)
ADP1047/ADP1048
SMART VOUT LOW LINE (VOL1) REGISTER
Table 131. Register 0xFE46—Smart VOUT Low Line (VOL1)
Bits
[15:11]
[10:0]
SMART VOUT LOW LINE (VOL2) REGISTER
Table 132. Register 0xFE47—Smart VOUT Low Line (VOL2)
Bits
[15:11]
[10:0]
SMART VOUT HIGH LINE (VOH1) REGISTER
Table 133. Register 0xFE48—Smart VOUT High Line (VOH1)
Bits
[15:11]
[10:0]
SMART VOUT HIGH LINE (VOH2) REGISTER
Table 134. Register 0xFE49—Smart VOUT High Line (VOH2)
Bits
[15:11]
[10:0]
SMART VOUT UPPER LIMIT (VOH) REGISTER
Table 135. Register 0xFE4A—Smart VOUT Upper Limit (VOH)
Bits
[15:11]
[10:0]
SMART VOUT SUPER HIGH LINE REGISTER
Table 136. Register 0xFE4B—Smart VOUT Super High Line
Bits
[15:11]
[10:0]
SYNC DELAY REGISTER
Table 137. Register 0xFE4C—SYNC Delay
Bits
[15:0]
Bit Name
RSVD
VOL1
Bit Name
RSVD
VOL2
Bit Name
RSVD
VOH1
Bit Name
RSVD
VOH2
Bit Name
RSVD
VOH
Bit Name
RSVD
Super high line
voltage
Bit Name
t
SYNC_DELAY
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
R/W
Description
Reserved.
These bits set the output voltage under low power mode operation with low line input.
Description
Reserved.
These bits set the output voltage under high power mode operation with low line input.
Description
Reserved.
These bits set the output voltage under low power mode operation with high line input.
Description
Reserved.
These bits set the output voltage under high power mode operation with high line input.
Description
Reserved.
These bits set the output voltage when the VAC input voltage is higher than the value set in
Register 0xFE4B.
Description
Reserved.
These bits set the input voltage value as a super high line limit.
Description
These bits set the additional delay between the external synchronization reference clock signal
and the rising edge of PWM. Each LSB corresponds to 80 ns resolution.
Rev. 0 | Page 76 of 84
Data Sheet
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