ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 87

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ADUC7121

Manufacturer Part Number
ADUC7121
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7121

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Sram (bytes)
8192Bytes
Gpio Pins
32
Adc # Channels
9

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TIMERS
The ADuC7121 has five general purpose timers/counters.
The five timers in their normal mode of operation can be either
free-running or periodic.
In free-running mode, the counter decrements/increments
from the maximum/minimum value until zero scale/full scale
and starts again at the maximum/minimum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero scale/full
scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its
value register (TxVAL). Timers are started by writing in the
control register of the corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero if counting down or full scale if counting
up. An IRQ can be cleared by writing any value to the clear
register of the particular timer (TxCLRI).
Table 121. Event Selection (ES) Numbers
ES
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
TIMER0—LIFETIME TIMER
Timer0 is a general-purpose, 48-bit count up, or a 16-bit count
up/down timer with a programmable prescaler. Timer0 is
clocked from the core clock, with a prescaler of 1, 16, 256, or
32,768. This gives a minimum resolution of 22 ns when the core
is operating at 41.78 MHz and with a prescaler of one. Timer0
can also be clocked from the undivided core clock, internal
32 kHz oscillator or external 32 kHz crystal.
Timer0
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
Timer4
Interrupt No.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Name
RTOS timer (Timer0)
GP Timer0 (Timer1)
Wake-up timer (Timer2)
Watchdog timer (Timer3)
GP Timer4 (Timer4)
IDAC Fault IRQ
Power supply monitor
Undefined
Flash Block 0
Flash Block 1
ADC
UART
SPI
I
I
I
I
External IRQ0
2
2
2
2
C0 master
C0 slave
C1 master
C1 slave
Rev. 0 | Page 87 of 96
In 48-bit mode, Timer0 counts up from zero. The current
counter value can be read from T0VAL0 and T0VAL1.
In 16-bit mode, Timer0 can count up or count down. A 16-bit
value can be written to T0LD that is loaded into the counter. The
current counter value can be read from T0VAL0. Timer0 has a
capture register (T0CAP) that can be triggered by a selected IRQ’s
source initial assertion. When triggered, the current timer value is
copied to T0CAP, and the timer keeps running. This feature can be
used to determine the assertion of an event with more accuracy
than by servicing an interrupt alone.
Timer0 reloads the value from T0LD either when TIMER0
overflows or immediately when T0ICLR is written.
Timer0 interface consists of six MMRs as listed in Table 122.
Table 122. Timer0 Interface MMRs
Name
T0LD
T0CAP
T0VAL0/T0VAL1
T0ICLR
T0CON
Timer0 Value Registers
T0VAL0 and T0VAL1 are 16-bit and 32-bit registers that hold
the 16 least significant bits and 32 most significant bits, respectively.
T0VAL0 and T0VAL1 are read-only registers. In 16-bit mode,
16-bit T0VAL0 is used. In 48-bit mode, both 16-bit T0VAL0
and 32-bit T0VAL1 are used.
Name:
Address:
Default value:
Access:
Name:
Address:
Default value:
Access:
T0VAL0
0xFFFF0304
0x0000
Read only
T0VAL1
0xFFFF0308
0x00000000
Read only
Description
16-bit register that holds the 16-bit value
loaded into the counter. Available only in
16-bit mode.
16-bit register that holds the 16-bit value
captured by an enabled IRQ event. Available
only in 16-bit mode.
TOVAL0 is a 16-bit register that holds the 16
least significant bits (LSBs).
T0VAL1 is a 32-bit register that holds the 32
most significant bits (MSBs).
T0VAL0 and T0VAL1 are read only. In 16-bit
mode, 16-bit T0VAL0 is used. In 48-bit mode,
both 16-bit T0VAL0 and 32-bit T0VAL1 are used.
8-bit register. Writing any value to this register
clears the interrupt. Available only in 16-bit
mode.
Configuration MMR.
ADuC7121

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