ADUC7121 Analog Devices, ADUC7121 Datasheet - Page 28

• Manufacturer Part Number: ADUC7121
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, ARM7TDMI MCU
• Manufacturer: Analog Devices

Specifications of ADUC7121

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Sram (bytes): 8192Bytes
• Gpio Pins: 32
• Adc # Channels: 9

ADuC7121
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the V
V
signal is −V
common mode (CM). The common mode is the average of the
two signals (V
two inputs are centered on, which results in the span of each
input being CM ± V
and its range varies with V
Inputs section).
The output coding is twos complement in fully differential
mode with
The output result is ±11 bits, but this is shifted by one bit to the
right. This allows the result in ADCDAT to be declared as a
signed integer when writing C code. The designed code transi-
tions occur midway between successive integer LSB values (that is,
1/2 LSB, 3/2 LSBs, 5/2 LSBs, …, FS − 3/2 LSBs). The ideal input/
output transfer characteristic is shown in Figure 14.
PADC0x/PADC1x Pins
The PADC0x and PADC1x pins are differential input channels
to the ADC that each have a programmable gain amplifier
(PGA ) on their front ends.
An external precision resistor converts the current to voltage and
the PGA then amplifies this voltage signal with gain up to 5 by
32 steps. The intention is to compensate the variation of the
detector diode responsivity and normalize optical power read
by the ADC. The external resistor is assumed 0.1% accuracy,
5 ppm. A 1 nF capacitor is shunted with the resistor to suppress
wideband noise. Select the resistor value such that the full-scale
voltage developed on the resistor is less than AV
typically 1.8 V.
The PGA is designed to handle 10 mV minimum input. To
minimize noise, bypass the ADC input buffer.
IN−
SIGN
BIT
). Therefore, the maximum amplitude of the differential
0 1111 1111 1110
0 1111 1111 1100
0 1111 1111 1010
0 0000 0000 0001
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 0000 0000 0000
1 LSB = 2 V
V
REF
= 2.5 V
Figure 14. ADC Transfer Function in Differential Mode
REF
IN+
to +V
REF
+ V
–V
/4096 or 2 × 2.5 V/4096 = 1.22 mV when
REF
REF
REF
1LSB =
IN−
/2. This voltage must be set up externally,
+ 1LSB
)/2, and is, therefore, the voltage that the
p-p (2 × V
REF
2 × V
IN+
VOLTAGE INPUT (V
4096
(see the Driving the Analog
and V
REF
REF
0LSB
IN−
). This is regardless of the
inputs (that is, V
IN
+ – V
IN
DD
+V
–)
REF
− 1.2 V, or
– 1LSB
IN+
−
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PADC0N is driven by a buffer to 0.15 V to keep the PGA from
saturation when the input current drops to zero. The buffer can
be disabled by setting the ADCCON Bit 14 so that the PADC0N
pin can be connected to the ground plane as well. This is the
same for the PADC1N pin.
The ADC needs to be placed in pseudo differential mode and
assumes that the negative input is close to ground.
All of the controls are independently set through register bits
for giving maximum flexibility to the user. Typically, users need
to take the following steps (using PADC0x as an example):
1.
2.
3.
4.
5.
6.
7.
8.
Other Input Channels
ADuC7121 contains seven extra ADC input pins. These pins
can also be configured as differential input pairs or single-ended
inputs, or pseudo differential inputs. The buffer and ADC are
configured independently from the input channel selection. Note
that the input range of the ADC input buffer is from 0.15 V to
AV
input buffer must be bypassed.
The ADuC7121 provides two pins for each thermistor input.
The negative input removes the error of the ground difference.
When selecting the thermistor input, always bypass the negative
side buffer to ensure that the amplifier is not saturated. Configure
the ADC to work in positive pseudo differential mode.
Besides these external inputs, the ADC can also select internal
inputs to monitor three power supplies: IOVDD, PVDD_IDAC0,
and PVDD_IDAC1. The voltage of the five IDAC outputs can
also be monitored by the ADC by selecting the required
channel in Register ADCCP. These internal signals are single-
ended and can select AGND/PGND/IOGND as the negative
input of the ADC via the ADCCN register.
Note that when monitoring IDAC outputs or PVDD_IDAC0,
PVDD_IDAC1, or IOVDD_MON, the buffer must be enabled
to isolate interference from ADC sampling.
An on-chip diode can also be selected to provide chip temperature
monitoring. The ADC can also select V
for calibration purposes.
PGA and Input Buffer
The PGA is a one stage, positive gain amplifier that is able to
accept input from 0.1 V to AV
should be at least 2.5 V. The gain of the PGA is from 1 to 5 with
32 linear steps. The PGA cannot be bypassed for the PADC0x
and PADC1x channels.
DD
Select PADC0N and PADC0P as the PGA input.
Select the PGA output as a MUX input.
Enable the PADC0N pin buffer.
Disable the ADC input buffer.
Set the proper gain value for the PGA.
Bypass the buffer.
Set the ADC to pseudo differential mode.
Start the conversion.
− 0.15 V; if the input signal range exceeds this range, the
DD
− 1.2 V, and the output swing
REF
and AGND as inputs